Why in the Design Timing Summery (synthesis) in Vivado i get WNS = inf?

Question

I want to make sure that my program works with a clock of at least 100ns. I have already set the timing constraint.

Answer 1

WNS=INF typically means ~ you do not have/ did not setup a clock.

Maybe you dont need a clock - is your circuit all combinatorial? If so, need to add registers and clock to get timing report to report a timed path.

If you circuit has FFs, clk and such already - make sure you tell Vivado (or Quartus) that your clock exists and is a specific frequency - some kind of create_clock constraint.