Category "vhdl"

May I use questasim synthesizer instead of quartus synthesizer to fit vhdl 2008

I'm attempting to synthesis VHDL-2008 to fit on a DE-10 lite fpga board. For the time being, I'm using Quartus II 21.10 lite edition which has drop support for

VHDL: Are enumerations in multiple type declarations named the same treated as the same value?

See the following simplified code example. The reason for trying to do this is do to reporting on missing FSM transitions to ST1 in return_to_states when retur

VHDL outputs all 'xxxx' for one specific case

My code has to work in 2 modes, mode 0 works without any problems, however mode 1 starting of the fist if statement implemented just shows xxx. all of the value

How to simulate Xilinx XADC in Questa SIM?

Is it possible to simulate Xilinx XADC in Questa Sim 10.6_1 simulator? I like to instantiate the XADC module in the top-level testbench module to overserve the

FSM enters impossible state

I have a FSM consisting of 3 states: STATIC, UP and DOWN. The FSM starts in the STATIC state and if I press the up arrow key, it will move to the UP state, ther

Use constants in VHDL and posterior synthesis

In VHDL, I know about constants and variables, but at the moment I have only used the integer or std_logic_vector data types with them. In order to analyse and

I tried writing UART VHDL code for loopback testing. Can anyone help me how to write a testbench for it

UART loopback testing code for an FPGA: -- -- Inputs/Outputs: -- -- SYS: -- I_clk - system clock - at least 16x baud rate for recieve --

VHDL Counter mod 60

I need help with this counter mod 60. Please help ! The T60 is the signal when count hit 59, 0 or 1 if is the case. Also when count hit 60, countget reseted to

Need to set default output, but it does not work

I got this code to compile and work, but all leds were on constantly. So I decided it needed to be defaulted, which is why I added: "011101111" to output in se

vunit, what are reset conditions between test case

I'm very confused about vunit testing, especially the link between tests and the way they are reset. Please take a look at next minimal example: device under te

VHDL wrapper for 1-wire core for DS18B20 temperature sensor

currently I am trying to write a VHDL wrapper for this Opencore Verilog module (1-wire master) so that I can send/receive from this temperature sensor (DS18B20)

VHDL 4-bit multiplier based on 4-bit adder

i am a bit new to VHDL and i try to learn by examples. So long story short i began with some basic examples like creating this Full Adder. entity FA is Port

Interface DHT22 to FPGA - elbert v2

Now i make a circuit to measure temperature and humidity, then display on LCD. This is my code for DHT22, i use Elbert V2. After genarating my project, it did

Adding Library to VHDL Project

I am trying to use fixed point numbers in my VHDL project, but I keep having trouble implementing the library (found here http://www.eda-stds.org/fphdl/fixed_pk

Other Categories