Category "vhdl"

vunit, what are reset conditions between test case

I'm very confused about vunit testing, especially the link between tests and the way they are reset. Please take a look at next minimal example: device under te

VHDL wrapper for 1-wire core for DS18B20 temperature sensor

currently I am trying to write a VHDL wrapper for this Opencore Verilog module (1-wire master) so that I can send/receive from this temperature sensor (DS18B20)

VHDL 4-bit multiplier based on 4-bit adder

i am a bit new to VHDL and i try to learn by examples. So long story short i began with some basic examples like creating this Full Adder. entity FA is Port

Interface DHT22 to FPGA - elbert v2

Now i make a circuit to measure temperature and humidity, then display on LCD. This is my code for DHT22, i use Elbert V2. After genarating my project, it did

Adding Library to VHDL Project

I am trying to use fixed point numbers in my VHDL project, but I keep having trouble implementing the library (found here http://www.eda-stds.org/fphdl/fixed_pk