VHDL: Are enumerations in multiple type declarations named the same treated as the same value?

Question

See the following simplified code example. The reason for trying to do this is do to reporting on missing FSM transitions to ST1 in return_to_states when return_to_states is of type All_states. Again this is highly simplified code to illustrate the question.

type All_states  is (ST1, ST2, ST3, ST4, SPI_write);
type Write_states  is (ST2, ST3, ST4, SPI_write);

signal FRAM_state : All_states  ;
singal return_to_state: Write_states  ;

pMain_SM : process(clk)
begin
if(rising_edge(clk)) then
    if(reset ='1') then
          FRAM_state <= ST1;
    else
         case FRAM_state is
when ST1 =>
       return_to_state  <= ST2;
       FRAM_state  <= SPI_Write;
when ST2 =>
       return_to_state  <= ST3;
      FRAM_state  <= SPI_Write;
when ST3 =>
       return_to_state  <= ST4;
      FRAM_state  <= SPI_Write;
when ST4 =>
       FRAM_state  <= ST1;
when SPI_Write =>
       FRAM_state  <= return_to_state ;