'VHDL outputs all 'xxxx' for one specific case
My code has to work in 2 modes, mode 0 works without any problems, however mode 1 starting of the fist if statement implemented just shows xxx. all of the values are input manually in the simulation file, so it should not have any dependences on the previous blocks that are used.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity floor_organiser is
port (mode : in bit;
route : integer range 0 to 30 := 0;
cf :in std_logic_vector (2 downto 0);
df1 :in std_logic_vector (2 downto 0);
df2 :in std_logic_vector (2 downto 0);
df3 :in std_logic_vector (2 downto 0);
df4 :in std_logic_vector (2 downto 0);
f1 :out std_logic_vector (2 downto 0);
f2 :out std_logic_vector (2 downto 0);
f3 :out std_logic_vector (2 downto 0);
f4 :out std_logic_vector (2 downto 0));
end entity;
architecture meow of floor_organiser is
signal vecup : std_logic_vector (15 downto 0) := "1000100010001000";
signal iup : integer range 0 to 15 := 15;
signal orderup : integer range 0 to 15 := 15;
signal vecdown : std_logic_vector (15 downto 0) := "1000100010001000";
signal idown : integer range 0 to 15:= 15;
signal orderdown : integer range 0 to 15:= 15;
signal aux : std_logic_vector (3 downto 0);
signal numsup : integer range 0 to 3 := 0;
signal numsdown : integer range 0 to 3 := 0;
signal final : std_logic_vector (15 downto 0);
signal ifinal : integer range 0 to 15 := 15;
signal finalup : integer range 0 to 15 := 15;
signal finaldown : integer range 0 to 15:= 15;
constant a : integer range 0 to 3 := numsup;
constant b : integer range 0 to 3 := numsdown;
begin
process(mode, cf, df1, df2, df3, df4) is
begin
if mode = '1' then
--df1
if cf<df1 then
vecup(iup) <= '0';
vecup(iup-1) <= df1(2);
vecup(iup-2) <= df1(1);
vecup(iup-3) <= df1(0);
iup <= iup-4;
elsif cf>df1 then
vecdown(idown) <= '0';
vecdown(idown-1) <= df1(2);
vecdown(idown-2) <= df1(1);
vecdown(idown-3) <= df1(0);
idown <= idown-4;
end if;
--df2
if cf<df2 then
vecup(iup) <= '0';
vecup(iup-1) <= df2(2);
vecup(iup-2) <= df2(1);
vecup(iup-3) <= df2(0);
iup <= iup-4;
elsif cf>df2 then
vecdown(idown) <= '0';
vecdown(idown-1) <= df2(2);
vecdown(idown-2) <= df2(1);
vecdown(idown-3) <= df2(0);
idown <= idown-4;
end if;
--df3
if cf<df3 then
vecup(iup) <= '0';
vecup(iup-1) <= df3(2);
vecup(iup-2) <= df3(1);
vecup(iup-3) <= df3(0);
iup <= iup-4;
elsif cf>df3 then
vecdown(idown) <= '0';
vecdown(idown-1) <= df3(2);
vecdown(idown-2) <= df3(1);
vecdown(idown-3) <= df3(0);
idown <= idown-4;
end if;
--df4
if cf<df4 then
vecup(iup) <= '0';
vecup(iup-1) <= df4(2);
vecup(iup-2) <= df4(1);
vecup(iup-3) <= df4(0);
iup <= iup-4;
elsif cf>df4 then
vecdown(idown) <= '0';
vecdown(idown-1) <= df4(2);
vecdown(idown-2) <= df4(1);
vecdown(idown-3) <= df4(0);
idown <= idown-4;
end if;
--ordering vecup
for i in 1 to 3 loop
for y in 1 to 3 loop
if (vecup(orderup) /= '1') and (vecup(orderup-4) /= '1') then
if vecup(orderup downto orderup-3) > vecup(orderup-4 downto orderup-7)then
aux <= vecup(orderup downto orderup-3);
vecup(orderup downto orderup-3) <= vecup(orderup-4 downto orderup-7);
vecup(orderup-4 downto orderup-7) <= aux;
orderup <= orderup - 4;
end if;
numsup <= numsup+1;
end if;
end loop;
orderup <= 15;
end loop;
--ordering vecdown
for i in 1 to 3 loop
for y in 1 to 3 loop
if (vecdown(orderdown) /= '1') and (vecdown(orderdown-4) /= '1') then
if vecdown(orderdown downto orderdown-3) < vecdown(orderdown-4 downto orderdown-7)then
aux <= vecdown(orderdown downto orderdown-3);
vecdown(orderdown downto orderdown-3) <= vecdown(orderdown-4 downto orderdown-7);
vecdown(orderdown-4 downto orderdown-7) <= aux;
orderdown <= orderdown - 4;
end if;
numsdown <= numsdown+1;
end if;
end loop;
orderdown <= 15;
end loop;
--final vector
for i in 0 to a loop
final(ifinal downto ifinal-3) <= vecup(finalup downto finalup-3);
ifinal <= ifinal - 4;
finalup <= finalup -4;
end loop;
for i in 0 to b loop
final(ifinal downto ifinal-3) <= vecdown(finaldown downto finaldown-3);
ifinal <= ifinal - 4;
finaldown <= finaldown -4;
end loop;
f1 <= final(14 downto 12);
f2 <= final(10 downto 8);
f3 <= final(6 downto 4);
f4 <= final(2 downto 0);
elsif mode = '0' then
f1 <= df1;
f2 <= df2;
f3 <= df3;
f4 <= df4;
end if;
end process;
end architecture;
The simulation looks like this: simulation
Sources
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