'wait statement without UNTIL clause not supported for synthesis: i wanted to delay my result by 10 ns seconds but this error keep showing

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Four_bit_Multiplier is
   port
   (
      Value1: in std_logic_vector(3 downto 0);
      Value2: in std_logic_vector(3 downto 0);
      Result: out std_logic_vector(7 downto 0)
   );
end Four_bit_Multiplier;

architecture Behavioral of Four_bit_Multiplier is

begin
    process is
    begin
     
    Result <= std_logic_vector(unsigned( Value1) * unsigned( Value2));
    
    wait for 10 ns;
    
    end process;
    
end  Behavioral;
vhdl


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