VHDL - (modelsim) - Fatal error that indicated during simulation

Question

my VHDL code i went to simulate this at modelsim but a fatal error occurs saying:

Fatal: (vsim-3734) Index value -1 is out of range 4 downto 0. Time: 0 ps Iteration: 0 Region: /carry_select_adder/P7(4) File: C:/Users/Theo/Documents/first/carry_select_adder.vhd Line: 62 FATAL ERROR while loading design Error loading design End time: 14:57:27 on May 22,2022, Elapsed time: 0:00:00 Errors: 1, Warnings: 2 Compile of carry_select_adder.vhd failed with 1 errors.*

Library IEEE;
Use IEEE.std_logic_1164.all;
Entity carry_select_adder is
port (X,V:In std_logic_vector (7 downto 0);
Cin:In std_logic;
Sum:Out std_logic_vector (8 downto 0);
Cout:Out std_logic);
End carry_select_adder;

Architecture structural of carry_select_adder is

Component adder4 is
port (A,B:In std_logic_vector (3 downto 0);
Ci:In std_logic;
S:Out std_logic_vector (3 downto 0);
Co:Out std_logic);
End component;

Component mux_2to1_5 is
port (S:In std_logic;
A,B:In std_logic_vector (4 downto 0);
Y:Out std_logic_vector (4 downto 0));
End component;

signal Sum0,P,O,K,L: std_logic_vector (3 downto 0);
signal Sum1,Sum2: std_logic_vector (3 downto 0);
signal S1,S2,S3: std_logic_vector (4 downto 0);

signal C3: std_logic;
begin
P1: for i In 3 downto 0 generate
    P(i) <= X(i);
End generate;

P2: for i In 3 downto 0 generate
    O(i) <= V(i);
End generate;

P3: for i In 7 downto 4 generate    
    K(i-4) <= X(i);
    L(i-4) <= V(i);
End generate;



FA: adder4 port map(P,O,Cin,Sum0,C3);


FA0: adder4 port map(K,L,'0',Sum1,S1(4));


FA1: adder4 port map(K,L,'1',Sum2,S2(4));

P5: for i In 3 downto 0 generate
    S1(i) <= Sum1(i);
End generate;

P6: for i In 3 downto 0 generate
    S2(i) <= Sum2(i);
End generate;

MUX0: mux_2to1_5 port map (C3,S1,S2,S3);

P7: for i In 8 downto 4 generate
    Sum(i) <= S3(i-5);
End generate;

P8: for i In 3 downto 0 generate
    Sum(i) <= Sum0(i);
End generate;


End Structural;