VHDL Error 10500 Code syntax errors in quartus (VHDL)

Question

I don't know what I'm doing wrong with this code.

Error (10500): VHDL syntax error at Gate.vhd(17) near text "signal"; expecting "end", or "(", or an identifier ("signal" is a reserved keyword), or a concurrent statement

This is my full code and if you have time please let me know what's wrong I would really appreciate it!

library ieee;
use ieee.std_logic_1164.all;
entity Gate is
port( 
    a, b, c : in std_logic;
    y : out std_logic
    );
end Gate;

architecture sample of Gate is




begin

signal w, x : std_logic;


w <= a or b; 
x <= b nand c; 
y <= w xor x;


end sample;