repetitive input/output entity declaration vhdl

Question

I've got multiple (same) input/output to declare :

B1_data_to_send         : in std_logic_vector(15 downto 0);
B1_start_transmission   : out std_logic;
B1_transmission_busy    : in std_logic;

B2_data_to_send         : in std_logic_vector(15 downto 0);
B2_start_transmission   : out std_logic;
B2_transmission_busy    : in std_logic;

B3_data_to_send         : in std_logic_vector(15 downto 0);
B3_start_transmission   : out std_logic;
B3_transmission_busy    : in std_logic;

B4_data_to_send         : in std_logic_vector(15 downto 0);
B4_start_transmission   : out std_logic;
B4_transmission_busy    : in std_logic;

B5_data_to_send         : in std_logic_vector(15 downto 0);
B5_start_transmission   : out std_logic;
B5_transmission_busy    : in std_logic;

B6_data_to_send         : in std_logic_vector(15 downto 0);
B6_start_transmission   : out std_logic;
B6_transmission_busy    : in std_logic;

I've got 30 block like this to create, is there a way to avoid this repetition and to create a generic block that I can instantiate with different names ?

Answer 1

Arrays are what you need here. First, you will need to create an array type of std_logic_vector in a package. If you're using VHDL 2008, it can simply be an unconstrained type:

package types_pkg is
  type slv_array_t is array(natural range <>) of std_logic_vector;
end package;

and then use this type in your entity:

use work.types_pkg.all;

entity your_entity is
  port (
    B_data_to_send       : in  slv_array_t     (1 to 30)(15 downto 0);
    B_start_transmission : out std_logic_vector(1 to 30);
    B_transmission_busy  : in  std_logic_vector(1 to 30)
  );
end entity;

Of course, any of the dimensions can come from a generic.

use work.types_pkg.all;

entity your_entity is
  generic (
    G_N_PORTS : natural;
    G_D_WIDTH : natural
  );
  port (
    B_data_to_send       : in  slv_array_t     (0 to G_N_PORTS-1)(G_D_WIDTH-1 downto 0);
    B_start_transmission : out std_logic_vector(0 to G_N_PORTS-1);
    B_transmission_busy  : in  std_logic_vector(0 to G_N_PORTS-1) 
  );
end entity;