Internal signal type error in Test Bench VHDL

Question

I want use internal signal of tag_mem entity in vivado in Test Bench.

Line with error in TB_tag_mem.vhd:

    alias chTagMem is << signal .tag_mem.chTagMem : chTagMem_line >>;

Signal in tag_mem (tag_mem.vhd):

    type chTagMem_line is array (natural range <>) of std_logic_vector (TAG_WIDTH downto 0);
    signal chTagMem     : chTagMem_line(CHAN_CNT - 1 downto 0);

When I run simulation, I see error in elaborate.log:

Starting static elaboration
ERROR: [VRFC 10-3763] type error near 'chtagmem' ; expected type 'chtagmem_line' [C:/Users/Mixen/CBDD/tag_mem/tag_mem.srcs/sim_1/new/TB_tag_mem.vhd:68]

ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit tb_tag_mem in library work failed.

How fix this?

Reproduce

TB_tag_mem.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.NUMERIC_STD.all;

entity TB_tag_mem is
--  Port ( );
end TB_tag_mem;

architecture Test of TB_tag_mem is

    component tag_mem is
    Port ( 
        clk : in STD_LOGIC
    );
    end component;
        
    -- for check
    type chTagMem_line is array (natural range <>) of std_logic_vector (5 downto 0);
    alias chTagMem is << signal .tag_mem.chTagMem : chTagMem_line >>;
    
begin
   sim: process begin
        report "TEST: Init";
        wait;
    end process sim;

end Test;

tag_mem.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;

entity tag_mem is
    Generic (
        WIDTH: integer := 5
    );
    Port ( 
        clk : in STD_LOGIC
    );
        
end tag_mem;

architecture Behavioral of tag_mem is
    type chTagMem_line is array (natural range <>) of std_logic_vector (WIDTH downto 0);
    signal chTagMem     : chTagMem_line(4 downto 0);

begin
end Behavioral;