Instantiate VHDL entity with 2D array from SystemVerilog

Question

There seems to be very little documentation on how to pass 2D arrays between VHDL and SystemVerilog. I have a port of the following type in VHDL:

package my_package is
    type my_array_t is array (natural range <>) of std_logic_vector(N-1 downto 0);
end my_package

entity my_entity is
    port(
        my_input  : in  my_array_t(M-1 downto 0);
        my_output : out my_array_t(M-1 downto 0);
    );
end entity;

And the following SystemVerilog signal:

wire [N-1:0] my_input_s[M-1:0];
wire [N-1:0] my_output_s[M-1:0];

I believe these two types are completely equivalent. However, I can't go between each other without getting errors. Instantiating the VHDL module from SystemVerilog:

my_entity my_entity_inst(
    .my_input(my_input_s),
    .my_output(my_output_s)
);

The error I get is "formal port 'my_input' of type 'my_array_t' does not match with actual type 'logic'", similarly for the output signal. I tried different combination of array types in SystemVerilog (fully packed, fully unpacked) but none works. Note that in my case, I don't have the freedom of changing the VHDL declaration, I must find a way to make it work solely from SystemVerilog. Thus, this question can't help me.

How do I instantiate my VHDL module from SystemVerilog in the most straightforward way?