In VHDL, how to write a 'not to be synthesized' routine to calculate 'values' used inside 'for generate'?

Question

I am trying to write VHDL code for a super generic Mux.

I am using a for - generate statement inside which are 3 more un-nested for-generate statements.

I want to increase the number of required iterations 'j' of the inner for-generate, depending on current value of the iterating variable 'i' of the outermost for-generate. I want the code as dynamic/generic as possible, so can't use 'if' statements to calculate 'j', as there would be infinite if statements.

So, I am looking to implement something like this:

G0 : for i in 0 to (gen_param1 - 1) generate
        
     L1: for j in 0 to ((gen_param2 / (2**(i+1))) - 1) generate

            M0: entity_name generic map ( ... )
                port map( Ip1 => d1, Ip2 => d2, ... , OP => some_signal(ROUTINE_CAL_J_MAX(gen_param2, j, i)
            
          end generate L1;

     end generate G0;

I don't need ROUTINE_CAL_J_MAX() to synthesize anything, it is only to calculate the iteration range of 'j', during compilation (/or whatever the right word for VHDL).

As per my knowledge I can't use 'function', 'procedure' or 'process' as they will be synthesized. So, that leaves nothing else I guess.

My specific needs for the ROUTINE( p2, i ) is to do this,

ROUTINE_CAL_J_MAX( param2, j, i )

       var1 = j;

       for n in 0 to i :
          var1 += ( param2/(2**n) );

return var1;

This is just to explain behavior of ROUTINE, pardon the syntax.

Thanks in advance!