'Component instance binding in configuration ignored
I have a testbench that should run with the appropriate simulation model for the target device (or a generic behavioural model), so I'm trying to use a configuration to map the component instance to the appropriate entity and its ports.
Somewhat minimal example:
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library std;
use std.env.finish;
entity sample is
port(
reset : in std_logic;
clk : in std_logic;
data : in std_logic_vector(7 downto 0)
);
end entity;
architecture rtl of sample is
component mem is
port(
clock : in std_logic;
address_a : in std_logic_vector(9 downto 0);
address_b : in std_logic_vector(9 downto 0);
q_a : out std_logic_vector(7 downto 0);
q_b : out std_logic_vector(7 downto 0);
wren_a : in std_logic;
wren_b : in std_logic;
data_a : in std_logic_vector(7 downto 0);
data_b : in std_logic_vector(7 downto 0)
);
end component;
signal address : unsigned(9 downto 0);
begin
address <= to_unsigned(0, 10) when reset = '1' else
address + 1 when rising_edge(clk);
storage : ram
port map(
clock => clk,
address_a => std_logic_vector(address),
q_a => open,
wren_a => '1',
data_a => data,
address_b => (others => '0'),
q_b => open,
wren_b => '0',
data_b => (others => '0')
);
end architecture;
entity tb_sample is
begin
end entity;
architecture sim of tb_sample is
signal reset : std_logic;
signal clk : std_logic := '0';
begin
reset <= '1', '0' after 1 us;
clk <= not clk after 10 ns;
process is
begin
wait for 10 us;
finish;
end process;
dut : sample
port map(
reset => reset,
clk => clk,
data => (others => '0')
);
end architecture;
configuration vendor of tb_sample is
for sim
for dut : sample
use entity work.sample
for storage : ram
use entity work.memory_ip(SYN);
end for;
end for;
end for;
end configuration;
My expectation would be that if I have the vendor's memory IP implementation available as work.memory_ip, and that has been compiled for ModelSim, it would be picked up. Everything compiles fine, but running gives
# ** Warning: (vsim-3473) Component instance "storage : ram" is not bound.
and the component isn't mentioned in the VCD file.
Is there anything I need to do to make ModelSim use the configuration?
Solution 1:[1]
From the use of std.env.finish this is from IEEE Std 1076-2008 or a newer revision.
All this shouldn't have compiled fine. The warning message is on architecture rtl of entity sample. It isn't clear without a bit of research or access to Modelsim whether or not elaboration of the design hierarchy is part of compilation (vcom) or simulation (vsim). It's a vsim error message, but there are analysis (compile) issues.
in the architecture rtl of entity sample the component declaration has a name mem and should be ram:
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
entity sample is
port (
reset: in std_logic;
clk: in std_logic;
data: in std_logic_vector(7 downto 0)
);
end entity;
architecture rtl of sample is
-- component mem is CHANGED to ram
component ram is
port (
clock: in std_logic;
address_a: in std_logic_vector(9 downto 0);
address_b: in std_logic_vector(9 downto 0);
q_a: out std_logic_vector(7 downto 0);
q_b: out std_logic_vector(7 downto 0);
wren_a: in std_logic;
wren_b: in std_logic;
data_a: in std_logic_vector(7 downto 0);
data_b: in std_logic_vector(7 downto 0)
);
end component;
signal address: unsigned(9 downto 0);
begin
address <= to_unsigned(0, 10) when reset = '1' else
address + 1 when rising_edge(clk);
storage:
ram
port map (
clock => clk,
address_a => std_logic_vector(address),
q_a => open,
wren_a => '1',
data_a => data,
address_b => (others => '0'),
q_b => open,
wren_b => '0',
data_b => (others => '0')
);
end architecture;
Entity tb_sample is missing a context clause and a component declaration for sample:
library ieee;
use ieee.std_logic_1164.all;
use std.env.finish;
entity tb_sample is
begin
end entity;
architecture sim of tb_sample is
signal reset: std_logic;
signal clk: std_logic := '0';
component sample is
port (
reset: in std_logic;
clk: in std_logic;
data: in std_logic_vector(7 downto 0)
);
end component;
begin
reset <= '1', '0' after 1 us;
clk <= not clk after 10 ns when now < 10 us;
process is
begin
wait for 10 us;
finish;
end process;
dut: sample
port map (
reset => reset,
clk => clk,
data => (others => '0')
);
end architecture;
These issues may be artifacts of attempting to produce a Minimal, Complete, and Verifiable example. With these changes those two entities and their architectures analyze into the working library (compile).
The configuration isn't quite right missing the block configuration for the architecture rtl of sample and can't be elaborated into a design hierarchy without an entity declaration (ip_memory) and it's architecture body (SYN). You haven't included any port name mapping between ram and ip_memory in the configuration.
configuration vendor of tb_sample is
for sim
for dut: sample
use entity work.sample;
for rtl
for storage: ram
use entity work.memory_ip(SYN);
end for;
end for;
end for;
end for;
end configuration;
This configuration would work if you had as a minimum:
library ieee;
use ieee.std_logic_1164.all;
entity memory_ip is
port (
clock: in std_logic;
address_a: in std_logic_vector(9 downto 0);
address_b: in std_logic_vector(9 downto 0);
q_a: out std_logic_vector(7 downto 0);
q_b: out std_logic_vector(7 downto 0);
wren_a: in std_logic;
wren_b: in std_logic;
data_a: in std_logic_vector(7 downto 0);
data_b: in std_logic_vector(7 downto 0)
);
end entity;
architecture SYN of memory_ip is
begin
end architecture;
analyzed into the working directory.
With all the bits and pieces analyzed into the working directory the configuration can be elaborated.
With the change made to the clock (clk) in the testbench to stop the clock after 10 us the configuration can be simulated in earlier VHDL revisions with the finish call translated to a wait statement.
And because VHDL is by and large portable and having placed all the design units in one design_file (here tb_sample.vhdl):
%: ghdl -a --std=08 tb_sample.vhdl
%: ghdl -e --std=08 vendor
%: ghdl -r vendor
simulation finished @10us
%:
It can analyze, elaborate and simulate (run) on other VHDL tools. The warning produced by Modelsim would show up here either trying to elaborate tb_sample as a design hierarchy or during elaboration of the configuration.
Without seeing all the design units before making a MCVe its not possible to see how the above issues came about.
The diagnostic messages for configuration declarations can be of poor quality. Configuration declarations are infrequently relied upon.
Solution 2:[2]
I found it.
The configuration name needs to be specified as the top-level entity to be simulated, i.e. in my case, that would be vsim … vendor.
It appears that entities and configurations form a single namespace here, which restricts naming.
Sources
This article follows the attribution requirements of Stack Overflow and is licensed under CC BY-SA 3.0.
Source: Stack Overflow
| Solution | Source |
|---|---|
| Solution 1 | |
| Solution 2 | Simon Richter |