'Can signal in std_logic have other value than 0 and 1?

I've been learning VHDL (mostly on my own) during my studies. I've heard that I should always cover all possible situations in case or if statements. My question is: is it technically possible for std_logic internal signal to have any other value than 0 or 1?

For example, is this possible:

signal or_gate : std_logic;

...
or_gate <= input1 or input2;
...
if(or_gate = '1') then
--led blinks fast
elsif(or_gate = '0') then
--led blinks slow
else
--led off
end if;

or there can only be led blinks or led off?

vhdl


Solution 1:[1]

for bit type we have just 0 and 1, but std_logic type except 0 and 1, support other values.

So the std_logic type can have the following values:

  • '1' : Logic 1
  • '0' : Logic 0
  • 'Z' : High impedance
  • 'W' : Weak signal, can’t tell if 0 or 1
  • 'L' : Weak 0, pulldown
  • 'H' : Weak 1, pullup
  • '-' : Don’t care
  • 'U' : Uninitialized
  • 'X' : Unknown, multiple drivers

Sources

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Source: Stack Overflow

Solution Source
Solution 1 Ali

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