'7 segment output signal is not correctly and expected, signal after high cant back to low
I created a 7 segment, there will have 4 "ras" with active low, while i am using the if statement to write, all the default input signal are set to active low. And the test bench had been set to correctly followed to active low. But the result look like after my ras0 is 0, and not set back to 1, which is off the signal. As can observe the pic below: enter image description here
1. Module
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.NUMERIC_STD.ALL;
entity Display_with_Signal is
Port ( ADDR : in STD_LOGIC_VECTOR (7 downto 0);
ras_temp0 : in STD_LOGIC;
ras_temp1 : in STD_LOGIC;
ras_temp2 : in STD_LOGIC;
ras_temp3 : in STD_LOGIC;
cas : in STD_LOGIC;
wr : in STD_LOGIC;
rd : in STD_LOGIC;
data : in STD_LOGIC_VECTOR (7 downto 0);
bank_LEDG0 : out STD_LOGIC:= '0'; --Row Bank signal
bank_LEDG1 : out STD_LOGIC:= '0'; --Row Bank signal
bank_LEDG2 : out STD_LOGIC:= '0'; --Row Bank signal
bank_LEDG3 : out STD_LOGIC:= '0'; --Row Bank signal
LEDG4 : out STD_LOGIC; --Cas signal
LEDG6 : out STD_LOGIC; --Write
LEDG7 : out STD_LOGIC; --Read
hex0 : out STD_LOGIC_VECTOR (6 downto 0);
hex1 : out STD_LOGIC_VECTOR (6 downto 0);
hex2 : out STD_LOGIC_VECTOR (6 downto 0);
hex3 : out STD_LOGIC_VECTOR (6 downto 0)
);
end Display_with_Signal;
architecture Behavioral of Display_with_Signal is
COMPONENT Seven_Segment
PORT(
addr : IN std_logic_vector(3 downto 0);
hex : OUT std_logic_vector(6 downto 0)
);
END COMPONENT;
begin
process (ras_temp0, ras_temp1, ras_temp2, ras_temp3) --signal for bank
begin
if ras_temp0 = '0' then
bank_LEDG0 <= '1';
elsif ras_temp1 = '0' then
bank_LEDG1 <= '1';
elsif ras_temp2 = '0' then
bank_LEDG2 <= '1';
elsif ras_temp3 = '0' then
bank_LEDG3 <= '1';
end if;
end process;
LEDG4 <= cas;
LEDG6 <= wr;
LEDG7 <= rd;
data1: Seven_Segment PORT MAP (
addr => data(3 downto 0),
hex => hex0
);
data2: Seven_Segment PORT MAP (
addr => data(7 downto 4),
hex => hex1
);
address1: Seven_Segment PORT MAP (
addr => ADDR(3 downto 0),
hex => hex2
);
address2: Seven_Segment PORT MAP (
addr => ADDR(7 downto 4),
hex => hex3
);
end Behavioral;
2. 7 Decoder
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Decoder is
Port ( reset : in STD_LOGIC;
clock : in STD_LOGIC;
CountIn : in STD_LOGIC_VECTOR (3 downto 0);
LEDs : out STD_LOGIC_VECTOR (6 downto 0)
);
end Decoder;
architecture Behavioral of Decoder is
begin
process(reset,clock)
begin
if (reset = '1') then --asynchronize reset
LEDs <= (others => '1'); --turn off all the lights
else
if (CountIn = "0000") then
LEDs <= "0000001"; --0
elsif (CountIn = "0001") then
LEDs <= "1001111"; --1
elsif (CountIn = "0010") then
LEDs <= "0010010"; --2
elsif (CountIn = "0011") then
LEDs <= "0000110"; --3
elsif (CountIn = "0100") then
LEDs <= "1001100"; --4
elsif (CountIn = "0101") then
LEDs <= "0100100"; --5
elsif (CountIn = "0110") then
LEDs <= "0100000"; --6
elsif (CountIn = "0111") then
LEDs <= "0001111"; --7
elsif (CountIn = "1000") then
LEDs <= "0000000"; --8
elsif (CountIn = "1001") then
LEDs <= "0001100"; --9
elsif (CountIn = "1010") then
LEDs <= "0001000"; --A
elsif (CountIn = "1011") then
LEDs <= "1100000"; --B
elsif (CountIn = "1100") then
LEDs <= "0110001"; --C
elsif (CountIn = "1101") then
LEDs <= "1000010"; --D
elsif (CountIn = "1110") then
LEDs <= "0110000"; --E
elsif (CountIn = "1111") then
LEDs <= "0111000"; --F
else
LEDs <= (others => '1'); --else turn off the seven segment
end if;
end if;
end process;
end Behavioral;
3. Test Bench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--USE ieee.numeric_std.ALL;
ENTITY tb_Display_with_Signal IS
END tb_Display_with_Signal;
ARCHITECTURE behavior OF tb_Display_with_Signal IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Display_with_Signal
PORT(
ADDR : IN std_logic_vector(7 downto 0);
ras_temp0 : IN std_logic;
ras_temp1 : IN std_logic;
ras_temp2 : IN std_logic;
ras_temp3 : IN std_logic;
cas : IN std_logic;
wr : IN std_logic;
rd : IN std_logic;
data : IN std_logic_vector(7 downto 0);
bank_LEDG0 : OUT std_logic;
bank_LEDG1 : OUT std_logic;
bank_LEDG2 : OUT std_logic;
bank_LEDG3 : OUT std_logic;
LEDG4 : OUT std_logic;
LEDG6 : OUT std_logic;
LEDG7 : OUT std_logic;
hex0 : OUT std_logic_vector(6 downto 0);
hex1 : OUT std_logic_vector(6 downto 0);
hex2 : OUT std_logic_vector(6 downto 0);
hex3 : OUT std_logic_vector(6 downto 0)
);
END COMPONENT;
--Inputs
signal ADDR : std_logic_vector(7 downto 0) := (others => '0');
signal ras_temp0 : std_logic := '0';
signal ras_temp1 : std_logic := '0';
signal ras_temp2 : std_logic := '0';
signal ras_temp3 : std_logic := '0';
signal cas : std_logic := '0';
signal wr : std_logic := '0';
signal rd : std_logic := '0';
signal data : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal bank_LEDG0 : std_logic;
signal bank_LEDG1 : std_logic;
signal bank_LEDG2 : std_logic;
signal bank_LEDG3 : std_logic;
signal LEDG4 : std_logic;
signal LEDG6 : std_logic;
signal LEDG7 : std_logic;
signal hex0 : std_logic_vector(6 downto 0);
signal hex1 : std_logic_vector(6 downto 0);
signal hex2 : std_logic_vector(6 downto 0);
signal hex3 : std_logic_vector(6 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Display_with_Signal PORT MAP (
ADDR => ADDR,
ras_temp0 => ras_temp0,
ras_temp1 => ras_temp1,
ras_temp2 => ras_temp2,
ras_temp3 => ras_temp3,
cas => cas,
wr => wr,
rd => rd,
data => data,
bank_LEDG0 => bank_LEDG0,
bank_LEDG1 => bank_LEDG1,
bank_LEDG2 => bank_LEDG2,
bank_LEDG3 => bank_LEDG3,
LEDG4 => LEDG4,
LEDG6 => LEDG6,
LEDG7 => LEDG7,
hex0 => hex0,
hex1 => hex1,
hex2 => hex2,
hex3 => hex3
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wr <= '1';
rd <= '0';
ADDR <= "10101010";
ras_temp0 <= '0';
ras_temp1 <= '1';
ras_temp2 <= '1';
ras_temp3 <= '1';
data <= "00010001";
wait for 100 ns;
wr <= '0';
rd <= '1';
ADDR <= "11111111";
ras_temp0 <= '1';
ras_temp1 <= '1';
ras_temp2 <= '1';
ras_temp3 <= '0';
data <= "00010001";
wait for 100 ns;
wait;
end process;
END;
Sources
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Source: Stack Overflow
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