'modelSim VHDL some input signals not appearing in object window

I'm working on a turbo decoding system on vhdl. The system is not outputing the expected result so I need to debug it. In the architecture of my decoder system, I'm instantiating the blocks components as follows:

inst_decoder : for i in 0 to MAX_BSIZE -1 generate

  signal llrs_valid_upper: std_logic ;
  signal llrs_in_upper : llrs_rec;
  signal llrs_valid_lower: std_logic;
  signal llrs_in_lower: llrs_rec;


begin


  -- get the corresponding llrs from the input_llr buffer, and set the llrs_valid to 1
  llrs_in_upper.system_llr <= input_llr(i); 
  llrs_in_upper.parity_llr <= input_llr(MAX_BSIZE+NUM_ENC_REGS+i);
  llrs_in_upper.extr_llr <= extr_upper_int(i);
  llrs_valid_upper <= input_llr_valid;

  inst_upper_algorithmic_block: component tcdec_algorithmic_block
    port map (
      clk => clk,
        rst => rst,
          en  => en_int,

          alpha_in => alpha_upper_int(i),
          beta_in => beta_upper_int(i+1),

          llrs_valid => llrs_valid_upper,
          llrs_in  => llrs_in_upper,

          init    => init,
          alpha_init => ALL_ZEROS,
          beta_init => ALL_ZEROS,

          extr_out  => extr_lower_int(de_il_table(i)),
          alpha_out => alpha_upper_int(i+1),
          beta_out => beta_upper_int(i)

    );

  llrs_in_lower.system_llr <= input_llr(il_table(i));
  llrs_in_lower.parity_llr <= input_llr(2*(MAX_BSIZE+NUM_ENC_REGS) + NUM_ENC_REGS + i);
  llrs_in_lower.extr_llr <= extr_lower_int(i);
  llrs_valid_lower <= input_llr_valid;

  inst_lower_algorithmic_block: component tcdec_algorithmic_block
    port map(
      clk => clk,
      rst => rst,
      en => en_int,

      alpha_in => alpha_lower_int(i),
      beta_in => beta_lower_int(i+1),

      llrs_valid => llrs_valid_lower,
      llrs_in => llrs_in_lower,

      init => init,
      alpha_init => ALL_ZEROS,
      beta_init => ALL_ZEROS,

      extr_out => extr_upper_int(il_table(i)),
      alpha_out => alpha_lower_int(i+1),
      beta_out => beta_lower_int(i)

    );  
end generate inst_decoder;

When trying to debug the design, some of the input signal for each block are not appearing, namely the rst signal, the llrs_in, the llrs_valid...

To make it weirder, the first block (for i=0, inst_upper_algorithmic_block) has all its input, the rest don't.

I tried restaring the computer, restarting modelSim, closing and opening the project with no use.

I tried also running the design with and without optimization, got the same result.

Any help is appreciated :)

vhdlmodelsim


Solution 1:[1]

Try compiling your design with -novopt -O0. Additionally, I believe you can manually add signals to the waveform via Tcl commands (need to test, as far as I remember, this works for signals missing from the object list.):

add wave "sim:/<testbench_name>/inst_upper_algorithmic_block/clk"

ModelSim will either add the signal or tell you why it can't be added.

But since things, "started to work", I believe you "fixed" your design (sometimes ModelSim doesn't helps us understanding what is wrong).

Solution 2:[2]

Delete the 'simulation' directory -> close modelsim -> reopen and simulate.

It showed the missing signals for me.

Solution 3:[3]

While starting a simulation, uncheck the box in the pop-up dialog box (as indicated by the black arrow). That worked for me. enter image description here

Sources

This article follows the attribution requirements of Stack Overflow and is licensed under CC BY-SA 3.0.

Source: Stack Overflow

Solution Source
Solution 1 suoto
Solution 2 vineeshvs
Solution 3 kb33

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