'How to send 2 different sets of data to simulation using one signal VHDL
I am building SPI master and I need to send 2 data packages to simulation. Here is my code
entity SPI_sas is
Port ( Clock : in STD_LOGIC;
MOSI : in STD_LOGIC;
OutData : out STD_LOGIC_VECTOR (9 downto 0);
OutDataLatch : out STD_LOGIC);
end SPI_sas;
architecture Behavioral of SPI_sas is
signal Output : std_logic_vector(9 downto 0);
begin
process (Clock)
variable cnt: integer :=0;
begin
if (falling_edge(Clock)) then
if cnt=10 then
cnt:=0;
OutDataLatch<='1';
else
OutDataLatch<='0';
cnt:=cnt+1;
Output<=Output(8 downto 0) & MOSI;
OutData<=Output;
end if;
end if;
end process;
end Behavioral;
and here is my testbench
entity tb_SPI_sas is
end tb_SPI_sas;
architecture Behavioral of tb_SPI_sas is
constant PERIOD : time := 10 ns;
signal Clock: STD_LOGIC:='0';
signal MOSI_Packet : STD_LOGIC_VECTOR (9 downto 0 ):="1010101010";
signal OutDataLatch : STD_LOGIC:='0';
signal MOSI_stimulus: STD_LOGIC:='0';
signal OutData : STD_LOGIC_VECTOR (9 downto 0 ):="0000000000";
signal Output : std_logic_vector(9 downto 0):="0000000000";
component SPI_sas is
port (
Clock : in STD_LOGIC;
MOSI : in STD_LOGIC;
OutData : out STD_LOGIC_VECTOR ( 9 downto 0 );
OutDataLatch : out STD_LOGIC);
end component SPI_sas;
begin
SPI_sas_inst: component SPI_sas
port map (
Clock => Clock,
MOSI => MOSI_stimulus,
OutData(9 downto 0) => OutData(9 downto 0),
OutDataLatch => OutDataLatch);
clk_proc: process
begin
Clock <= '0';
wait for PERIOD/2;
Clock <= '1';
wait for PERIOD/2;
end process clk_proc;
stimuli_proc: process (Clock)
variable cnt: integer :=0;
begin
if (rising_edge(Clock)) then
if cnt=10 then
cnt:=0;
else
cnt:=cnt+1;
MOSI_stimulus<=MOSI_Packet(0);
MOSI_Packet<='0' & MOSI_Packet(9 downto 1);
end if;
end if;
end process stimuli_proc;
end Behavioral;
After MOSI_PACKET is sent, I need to send different 10bits to the same packet to write it into OutData. Any ideas?
Sources
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Source: Stack Overflow
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