I have a circuit like this module control(input clk, output out); reg [63:0] r0 = 1, r1 = 2, r2 = 3, r3 = 4, r4 = 5; always @ (posedge clk) begin
I have installed xilinx ISE 10.1, 13.2 and 14.7.My code synthesizes but PlanAhead not opening on windows 10 64-bit.I googled and find a solution of replacing rd
I have a FSM consisting of 3 states: STATIC, UP and DOWN. The FSM starts in the STATIC state and if I press the up arrow key, it will move to the UP state, ther
I'm trying to install Xilinx Vivado 2021.1 on a Windows VM (Win10 20H2) automatically / fully unattended. I have tried steps from Xilinx Installation documentat
I am supposed to create 4 bit full adder verilog code in vivado.But when I try to test in the simulation.It give me z and x output.Which part of code I have to
In Vivado I succesfully made a simple blockdiagram to control the LEDs of my Zybo board. I can observe that the offset address for my LEDs is: 0x4120 0000 and t