I am working on an arm64 based board, running on Linux (Ubuntu 18.04). On the other end of this device, there is an FPGA connected via PCIe which is endpoint an
Recently I'm searching for info about if PCIe devices are involved in the uefi secure boot, and if so, how it is done. From the uefi specification, the main boo
Where I can find info on AMD Ryzen CPUs and how they expect MSI address/data to be programmed? The Intel manual is crystal clear in its description (pictured be
I know that the base address register (BAR) in PCI configuration space defines the start location of a PCI address, but how does the size of this region get est