Why my simulation with clock in ModelSim cannot work?

Question

I am writing a counter using VHDL on quatus. And below is my code: This is code for a flip_flop:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity ff is
    port(
        clk, rst: in std_logic;
        n0, n1: buffer std_logic_vector(3 downto 0)
    );
end ff;

architecture arch of ff is
    signal cnt: integer :=0;
begin
    process(clk, rst)
    begin
        if(rst = '0') then
            n0 <= "0000";
            n1 <= "0000";
            cnt <= 0;
        elsif (clk'event and clk = '1') then
            if (n0 = "1001") then
                n0 <= "0000";
                if(n1 = "0101") then
                    n1 <= "0000";
                else
                    n1 <= n1 + 1;
                end if;
            else
                n0 <= n0 + 1;
            end if;
        end if;
    end process;
end arch;

And this is translation code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity digit is
    port(
        number: in std_logic_vector(3 downto 0);
        display: out std_logic_vector(6 downto 0)
    );
end digit;

architecture arch of digit is
begin
    process(number)
    begin
        case number is
            when "0000"=>display<="1111110";
            when "0001"=>display<="0110000";
            when "0010"=>display<="1101101";
            when "0011"=>display<="1111001";
            when "0100"=>display<="0110011";
            when "0101"=>display<="1011011";
            when "0110"=>display<="1011111";
            when "0111"=>display<="1110000";
            when "1000"=>display<="1111111";
            when "1001"=>display<="1110011";
            when "1010"=>display<="1110111";
            when "1011"=>display<="0011111";
            when "1100"=>display<="1001110";
            when "1101"=>display<="0111101";
            when "1110"=>display<="1001111";
            when "1111"=>display<="1000111";
            when others=>display<="0000000";
        end case;
    end process;
end arch;

And this is my counter code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity basic_counter is
    port(
        clk, rst: in std_logic;
        out1, out0: out std_logic_vector(6 downto 0)
    );
end basic_counter;

architecture arch of basic_counter is
    signal n0, n1: std_logic_vector(3 downto 0);
    component ff
        port(
            clk, rst: in std_logic;
            n0, n1: buffer std_logic_vector(3 downto 0)
        );
    end component;
    component digit
        port(
            number: in std_logic_vector(3 downto 0);
            display: out std_logic_vector(6 downto 0)
        );
    end component;
begin 
    basic_ff: ff port map(clk=>clk, rst=>rst, n0=>n0, n1=>n1);
    digit_1: digit port map(number=>n0, display=>out0);
    digit_2: digit port map(number=>n1, display=>out1);
end arch;

I write a simulation code for ModelSim and here is my code:

-- Testbench created online at:
--   https://www.doulos.com/knowhow/perl/vhdl-testbench-creation-using-perl/
-- Copyright Doulos Ltd

library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;

entity basic_counter_tb is
end;

architecture bench of basic_counter_tb is

  component basic_counter
    port(
        clk, rst: in std_logic;
        out1, out0: out std_logic_vector(6 downto 0)
    );
  end component;

  signal clk, rst: std_logic;
  signal out1, out0: std_logic_vector(6 downto 0) ;
  constant period: time := 20ns;
  signal num: integer := 0;

begin

  uut: basic_counter port map ( clk  => clk,
                                rst  => rst,
                                out1 => out1,
                                out0 => out0 );

  stimulus: process
  begin
  
    -- Put initialisation code here
     rst <= '1';
     while(num < 90) loop
        clk <= '0';
        wait for period/2;
        clk <= '1';
        wait for period/2;
        num <= num + 1;
    end loop;
   -- Put test bench stimulus code here

    wait;
  end process;


end;

But the result is that out0 and out1 is always 0, but clk and rst and number is right. Where did I do wrong? Is there anything wrong with my counter code or simulation code?

Answer 1

If anyone finds this in the future, the answer is to extend your greetingTimeout. The connection is established but the greeting is never received because it times out too fast.