Why cant we write data from 2D array logic to 1D array in system verilog?

Question

module RegisterFile(ReadRegister1, ReadRegister2, WriteRegister, WriteData, RegWrite, ReadData1, ReadData2);
    input [4:0] ReadRegister1, ReadRegister2, WriteRegister;
    input [31:0] WriteData;
    input RegWrite;
    output reg[31:0] ReadData1, ReadData2;
    reg [31:0] mem[0:31];
    always @(ReadRegister1, ReadRegister2, WriteRegister, WriteData, RegWrite)begin
        if(RegWrite)
            mem[WriteRegister] <= WriteData;
        mem[0]<=0;
        ReadData1 <= mem[ReadRegister1];
        ReadData2 <= mem[ReadRegister2];
    end
endmodule

As you can see we send data from mem to ReadData 1 and 2 in always block but at the wave form ReadData 1 and 2 are 32'bx and they don't receive data from mem , by the way mem[ReadRegister1] mem[ReadRegister2] have valid data and if I write the code like this it works : ReadData1 <= 0; or ReadData1 <= 1;. I am sure other stuffs have valid data. so what is the problem with ReadData1 and ReadData2?