'Unexpected Xs in the result of addition of two logic signals

I have a code where two signals are added. Only top bits of the signals are X. Bottom bits are 0s. But, the result has all Xs. I would expect the bottom bits to be 0s in the result.

logic [3:0] a; // 4'bxx00
logic [3:0] b; // 4'bxx00
logic [4:0] c;

assign c = a + b; // Results in c = 4'bxxxxx

I am trying to understand why the bottom 2 bits are x in the result.

system-verilog


Solution 1:[1]

This behavior is specified in IEEE Std 1800-2017, section 11.4.3 Arithmetic operators:

For the arithmetic operators, if any operand bit value is the unknown value x or the high-impedance value z , then the entire result value shall be x .

The expression a + b contains an arithmetic operator: +

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