System verolog interface with parameters

Question

I'm trying to build an interface to connect two modules. the interface is in the next format:

interface my_if #( 
    parameter H_WIDTH = 64,
    parameter L_WIDTH = 8
);
logic [H_WIDTH -1:0]  a;
logic [L_WIDTH -1:0]  b;
logic                 ready;
modport in ( input a, input b, output valid);
modport out( output a, output b, input ready);
endinterface;

I need to connect two modules using this interface, while I have different parameters of address and index for every connection (for example, 3 my_if interfaces are connecting my two modules, but every one of them has a different address and index params). how I can make this work?

Answer 1

Use a maximum footprint approach with wrapper modules. Instantiate each of the modules that need to be connected in its own wrapper that uses the interface to create multiple ports. Parameterize each of the interfaces at the maximum size used in the design. Use another set of parameters (not associated with the interface) to specify size of the vectors needed inside each wrapper for my_module_x (like a bus ripper). The the design consists of my_module_1, my_module_2, my_wrapper_1, my_wrapper_2. Wrapper modules use interface style ports, non-wrapper modules (instantiated in the wrapper) do not use the interface port (they use parameterized vector style ports). Each my_module_x (non-wrapper) has a unique parameterization to access a unique slice of the maximal size signal-vector in the interface. For each module my_module_x is instantiated inside my_wrapper_x.

Put the parameterization for everything associated with this in a SV package, import the package to all the related modules, so that the sizes are controlled at one place in the design (the package).

There is overhead to this approach, it might pay for your design where there are a multiple related but not exactly the same modules which share the same interfaces, with different sizing.