System Verilog Interface Array as Port Parameter

Question

The code:

interface a_if;
    logic foo;
endinterface

interface b_if;
    a_if a();
endinterface

module y(a_if a);
    logic bar;
endmodule

module z();
    b_if b();
    y y(b.a);
    logic lex;
    assign lex = b.a.foo;
endmodule

works as expected, including passing interface "b.a" as a parameter to module "y". But the code:

interface a_if;
    logic foo;
endinterface

interface b_if;
    a_if a();
endinterface

module y(a_if a);
    logic bar;
endmodule

module z();
    b_if b[2]();
    y y(b[0].a);
    logic lex;
    assign lex = b[0].a.foo;
endmodule

fails (in NCV) with the message:

xmelab: *E,CUIOAI (./top.sv,37|10): Illegal interface port connection through a generate or array instance (z.b.a) .
module y(a_if a);

Accessing "b[0].a.foo" in the assign to "lex" is fine, but passing "b[0].a" as a parameter to module "y" is flagged as illegal. Is this a LRM limitation, or and NCV limitation?