system verilog: for loop index variable issue

Question

`timescale 1ns / 1ps

module param_right_shifter

# (parameter N = 3)
(
    input logic [$clog2(N)-1:0] a, // input
    input logic [N-1:0] amt, // shift bits
    output logic [$clog2(N)-1:0] y // output
);

logic [$clog2(N)-1:0][N:0] s;
logic [$clog2(N)-1:0] placeholder = a;
localparam bit_num = $clog2(N)-1;


always_comb
begin
        for(int i = 0; i < N; i++)
        begin
                if (i == 0)
                begin
                    s[i] = amt[i] ? {placeholder[i], placeholder[bit_num:2**i]} : placeholder; 
                    placeholder = s[i];  
                      
                end
                
                else
                
                begin
                    s[i] = amt[i] ? {placeholder[$clog2(N)-1:0], placeholder[bit_num:2**i]} : placeholder;
                    placeholder = s[i];
                end
        end
end

endmodule

I am having an issue with referencing the 'i' variable. It says that 'range must be bounded by constant expressions'. I am unsure of how to resolve.

Answer 1

Try below. I am assuming N is will have a constant value throughout the simulation. Please note that placeholder is driven by all bits of s so here placeholder will settle to s[N-1].

genvar i;
   
   generate
    for(i = 0; i < N; i++)
    begin
      
      if (i == 0)
      begin
        always_comb
        begin
          s[i] = amt[i] ? {placeholder[i], placeholder[bit_num:2**i]} : placeholder; 
          placeholder = s[i];  
         end   
      end 
   
      else     
      begin
        always_comb
        begin
         s[i] = amt[i] ? {placeholder[$clog2(N)-1:0], placeholder[bit_num:2**i]} : placeholder;
         placeholder = s[i];
        end
     end
   end

 endgenerate