$sformatf in SystemVerilog is not printing Hyperlinks on stdout

Question

The output of this SystemVerilog code should print hyperlinks on stdout that are not appearing, but it is capturing those hyperlinks in the file.

module top;
string res="some string";
string id="ID1";
string name1="Ram";
string name2="Singh";
string filename="test.sv";
int line=3;
string verbocity="High";
int fd1;

initial begin
res=$sformatf("<message ctxt=\"%s\" kind=\"%s\" id=\"%s\" location=\"%s:%0d\" verbosity=\"%s\" time=\"%0t\">%s</message>\n",name1,name2,id,filename,line,verbocity,$realtime,res);
$display(res);
fd1 = $fopen("data_txt", "w");
$fwrite(fd1, "%s\n", res);
$fclose(fd1);
end
endmodule

Answer 1

Your simulator should show the formatted string on stdout. Since it does not, there is a bug in the simulator you are using.

For example, with Synopsys on EDA playground, I see the following on stdout:

<message ctxt="Ram" kind="Singh" id="ID1" location="test.sv:3" verbosity="High" time="0">some string</message>

However, with Cadence, I see:

some string

This is the original value of res, without the formatting. This is a bug in the Cadence simulator. Three other simulators show the formatting (Synopsys, Mentor, Aldec).