RISCV32 vs RISCV64

Question

What are the differences between Riscv32 & Riscv64? I have been looking into the ISA docs, but cannot find it mentioned clearly anywhere, so pretty confused now.

I cannot find any docs about this from google, unfortunately. Any pointer?

Answer 1

RISC V has lots of options. RV32I and RV64I are base instruction sets, 32-bit and 64-bit respectively.  There is also a 128 bit version, RV128I, and, a smaller 32-bit version RV32E, which has only 16 general purpose registers, whereas the others have 32 registers.

To the base instructions sets, they add optional extensions, e.g. for floating point, multiply and divide, etc.., so like RV32IMAC is based on RV32I with the M, A, and C extensions.

The main difference between RV32I, RV64I, and RV128I is the width of the registers, 32, 64, or 128 bits in width.

There are some opcode differences as well.  The larger widths adds a few instructions to deal with the larger sizes.  RV64I, for example, uses the same opcode as RV32I for add, but means 64-bit add instead of 32-bit add, while there is a new opcode in RV64I for doing 32-bit only add (addw).  RV64I uses the same opcodes as RV32I for load and stores, though includes new opcodes for loading/storing 64-bit values.

See also:

• https://content.riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf
• https://www.cnx-software.com/2019/08/27/risc-v-bases-and-extensions-explained/
• https://content.riscv.org/wp-content/uploads/2018/05/13.15-13-50-Talk-riscv-base-isa-20180507.pdf

Answer 2

Risc 64-bit architecture has the same Instruction length (32bits) but the registers of the CPU are 64 bits wide instead of being 32 bits wide as in risc 32-bit versions.