'Qflow RTL2GDS flow of Rocket Chip fails at synthesis
I am attempting to generate an ASIC GDS using an open-source design flow. To this point, I have generated Verilog code from Rocket Chip generator. I am attempting to take this Verilog code, run it through Qflow, and generate a GDS.
After installing Qflow and the dependencies, I attempt the flow using the file freechips.rocketchip.system.DefaultConfig.v and the module ExampleRocketSystem. The flow fails almost immediately at synthesis. The console gives the error Qflow synthesis failed to generate an output .v file. The log file gives the error "ERROR: Value conversion failed: ``1 'd0'".
What is the meaning of this error? Is this the correct procedure to generate the GDS layout from Rocket Chip?
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