Category "register-transfer-level"

Divide by a number which is not power of 2 in Verilog RTL coding

For multiplication and division, we can use the left and right shifts. x>>2 // it will right shift by 2. ---> 2^2=4. (Multiply by 4 or divide by 4, de

System Verilog always_latch vs. always_ff

I am confused about the usage of statements always_ff and always_latch. The former would be used as: always_ff @ (posedge clk) begin a <= b; end while t