'Makefile conditional OR for definitions

I have a Makefile with 2 ifdef conditions that perform same action when that particular config is selected.

     #ifdef A
     //perform C
     #endif /* A */

     #ifdef B
     //perform C
     #endif /* B */

     #ifdef A || B
     //perform C
     #endif

Last code block is not working. What is the right way to execute it in Makefile?

Solution 1:^[1]

#ifdef and #endif are not make conditionals. You probably want:

ifdef A
# whatever if make variable A is defined
AB := defined
endif

ifdef B
# whatever if make variable B is defined
AB := defined
endif

ifeq ($(AB),defined)
# whatever if the make variable A or B is defined
endif

Note that ifdef A is not the same as ifneq ($(A),). So, if you want to test these variables not for definition but for emptiness, you probably want:

ifneq ($(A),)
# whatever if the value of make variable A is non-empty
endif

ifneq ($(B),)
# whatever if the value of make variable B is non-empty
endif

ifneq ($(A)$(B),)
# whatever if the value of make variable A or B is non-empty
endif

Solution 2:^[2]

Here's one way to do it using a variant of the technique I proposed in a comment:

# De Morgan's Law: (!a && !b) == !(a || b)
ifndef A
  ifndef B
    NEITHER_A_NOR_B_DEFINED :=
  endif
endif

ifndef NEITHER_A_NOR_B_DEFINED
  # Perform C
endif

Sources

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Solution	Source
Solution 1
Solution 2	Andreas

'Makefile conditional OR for definitions

Solution 1:[1]

Solution 2:[2]

Sources

Related Questions

Solution 1:^[1]

Solution 2:^[2]