'Is there any way to unroll Verilog generate for-loop while keep the code largely readable?

I'm working on a chunk of code that involves many generate for-loops. I fear I could be making a mistake, so I'd like to see its equivalent form.

As an example, I expect a tool to translate this:

genvar i;
    generate
        for (i = 0; i < PIXELS_IN_BATCH; i = i + 1)
        begin
            always @(*)
            begin
                b[i]=a[i*PIXELS_IN_BATCH];
            end
        end
    endgenerate

...to something like this:

always @(*)
            begin
                b[0]=a[0*PIXELS_IN_BATCH];
            end
always @(*)
            begin
                b[1]=a[1*PIXELS_IN_BATCH];
            end

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'Is there any way to unroll Verilog generate for-loop while keep the code largely readable?

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