How to use regs to modify wires?

Question

I am kind of new to Verilog and was wondering how I can modify wires. I know that you cannot modify wires inside always blocks.

I've seen something like this where you can declare some regs and assign the wire to those regs (which you can then modify the reg to modify the wire?)

module something
#(parameter D_W = 8)
(
    input  wire clk,
    input  wire rst,

    output wire valid,
    output wire [D_W-1:0] data,
);

reg valid_rg = 0;
reg [D_W-1:0] data_rg = 0;
    
assign valid = valid_rg;
assign data  = data_rg;

I was wondering how to do something like that for a wire like:

wire    [7:0] wire_a  [7:0];

Initially my guess would be to have something like this

reg [7:0] wire_a_rg [7:0];
assign wire_a[7:0] = wire_a_rg[7:0];

But I have a feeling it might be wrong. How could I approach this?