How to use only one ADC channel on MAX10

Question

I have an ADC core

component adc_qsys is
port (
    adc_1_command_valid          : in  std_logic                     := '0';              
    adc_1_command_channel        : in  std_logic_vector(4 downto 0)  := (others => '0');            
    adc_1_command_startofpacket  : in  std_logic                     := '0';            
    adc_1_command_endofpacket    : in  std_logic                     := '0';            
    adc_1_command_ready          : out std_logic;                                        
    adc_1_response_valid         : out std_logic;                                        
    adc_1_response_channel       : out std_logic_vector(4 downto 0);                    
    adc_1_response_data          : out std_logic_vector(11 downto 0);                    
    adc_1_response_startofpacket : out std_logic;                                        
    adc_1_response_endofpacket   : out std_logic;                                     
    clk_clk                      : in  std_logic                     := '0';             
    reset_reset_n                : in  std_logic                     := '0'              
);
end component adc_qsys;

U_ADC_SYS : adc_qsys 
port map 
(
    clk_clk        => s_pll_clk_10M, 
    reset_reset_n  => '1', 

    adc_1_command_valid          => adc1_com_valid, 
    adc_1_command_channel        => adc1_com_channel, 
    adc_1_command_startofpacket  => adc1_com_startofpacket,
    adc_1_command_endofpacket    => adc1_com_endofpacket, 
    adc_1_command_ready          => adc1_com_ready,
    adc_1_response_valid         => adc1_resp_valid,
    adc_1_response_channel       => adc1_resp_channel,
    adc_1_response_data          => adc1_resp_data, 
    adc_1_response_startofpacket => adc1_resp_startofpacket,
    adc_1_response_endofpacket   => adc1_resp_endofpacket
);

When I used the whole port ADC1_IN1 - ADC1_IN8 was no problem. Now I want to use only one channel - ADC1_IN1 so I set only CH1 active in the core.

However I get the errors while compiling

Error (176310): Can't place multiple pins assigned to pin location Pin_7 (IOPAD_X0_Y37_N21) Info (176311): Pin LED_CMD[5] is assigned to pin location Pin_7 (IOPAD_X0_Y37_N21) Info (176311): Pin ~ALTERA_ADC1IN2~ is assigned to pin location Pin_7 (IOPAD_X0_Y37_N21) Error (176310): Can't place multiple pins assigned to pin location Pin_8 (IOPAD_X0_Y36_N14) Info (176311): Pin LED_CMD[6] is assigned to pin location Pin_8 (IOPAD_X0_Y36_N14) Info (176311): Pin ~ALTERA_ADC1IN3~ is assigned to pin location Pin_8 (IOPAD_X0_Y36_N14) Error (176310): Can't place multiple pins assigned to pin location Pin_10 (IOPAD_X0_Y36_N21) Info (176311): Pin LED_CMD[7] is assigned to pin location Pin_10 (IOPAD_X0_Y36_N21) Info (176311): Pin ~ALTERA_ADC1IN4~ is assigned to pin location Pin_10 (IOPAD_X0_Y36_N21) Error (176310): Can't place multiple pins assigned to pin location Pin_11 (IOPAD_X0_Y35_N14) Info (176311): Pin LED_CMD[8] is assigned to pin location Pin_11 (IOPAD_X0_Y35_N14) Info (176311): Pin ~ALTERA_ADC1IN5~ is assigned to pin location Pin_11 (IOPAD_X0_Y35_N14) Error (176310): Can't place multiple pins assigned to pin location Pin_12 (IOPAD_X0_Y35_N21) Info (176311): Pin LED_CMD[9] is assigned to pin location Pin_12 (IOPAD_X0_Y35_N21) Info (176311): Pin ~ALTERA_ADC1IN6~ is assigned to pin location Pin_12 (IOPAD_X0_Y35_N21) Error (176310): Can't place multiple pins assigned to pin location Pin_13 (IOPAD_X0_Y34_N14) Info (176311): Pin LED_TEST is assigned to pin location Pin_13 (IOPAD_X0_Y34_N14) Info (176311): Pin ~ALTERA_ADC1IN7~ is assigned to pin location Pin_13 (IOPAD_X0_Y34_N14) Error (176310): Can't place multiple pins assigned to pin location Pin_14 (IOPAD_X0_Y34_N21) Info (176311): Pin LED_FLTn is assigned to pin location Pin_14 (IOPAD_X0_Y34_N21) Info (176311): Pin ~ALTERA_ADC1IN8~ is assigned to pin location Pin_14 (IOPAD_X0_Y34_N21)

How can I resolve the problem?

Answer 1

Looks Like you have a second module which has ports LED_CMD and LED_TEST that are using the same FPGA outputs. Take a look at your constraints/IO placement and move the other module to some other pins. That should fix it.

You could use the same bank for 2 different modules assuming the outputs are the same IO spec (LVCMOS33 etc.) as long as multiple outputs don't map to the same pin. Especially here, if you're only using 1 channel of the ADC, there's no reason for the other pins in the bank to not be used.