how many cache line are transmit from memory to l1 cache

Question

here is my computer cache config

LEVEL1_ICACHE_SIZE                 32768
LEVEL1_ICACHE_ASSOC                8
LEVEL1_ICACHE_LINESIZE             64
LEVEL1_DCACHE_SIZE                 32768
LEVEL1_DCACHE_ASSOC                8
LEVEL1_DCACHE_LINESIZE             64
LEVEL2_CACHE_SIZE                  1048576
LEVEL2_CACHE_ASSOC                 16
LEVEL2_CACHE_LINESIZE              64
LEVEL3_CACHE_SIZE                  34603008
LEVEL3_CACHE_ASSOC                 11
LEVEL3_CACHE_LINESIZE              64
LEVEL4_CACHE_SIZE                  0
LEVEL4_CACHE_ASSOC                 0
LEVEL4_CACHE_LINESIZE              0

here is my code:

#include <stdlib.h>

#define MISS 39321600


int main(){
    int *p = (int*)malloc(MISS * sizeof(int));
    int i;
    for(i=0; i<MISS; i++) {
        p[i] = 1;
    }
}

here is gcc version: gcc version 8.3.1 20190604

compile cmd: g++ main.cpp

cpu: Intel(R) Xeon(R) Platinum 8163 CPU @ 2.50GHz

then，perf it with cmd : perf stat -e cache-misses ./a.out

the cache-miss count is 400000 around

when i expect is 39321600/(64/4)=2457600 around

is 2457600/400000≈6 cache line get from memory once?