'Detect posedge for sync signal [Without using @posedge signal]

I'm trying to detect the posedge of a synchronous signal, but I don't know how to implement it relative to the clock [Without using @posedge signal]. Can I implement it like @(posedge clk iff -----)?

verilogsystem-verilog


Sources

This article follows the attribution requirements of Stack Overflow and is licensed under CC BY-SA 3.0.

Source: Stack Overflow

Solution Source

Related Questions

Verilog DUT System Verilog testbench: output to wire assignment 1s replaced with Xs

Verilog DUT System Verilog testbench: output to wire assignment 1s replaced with Xs

System Verilog always_latch vs. always_ff

How to write a module with variable number of ports in Verilog

How can I use foreach and fork together to do something in parallel?

I wrote this code in Verilog and there are no error messages, but it doesn't work

FPGA bitfile acting different with the simulation

How do I fix "Error: Illegal range in part select"?

Signal assignments from multiple if statements

Getting output of convolutional PE as XXX instead of a number?

Unexpected Xs in the result of addition of two logic signals

Cross coverage binsof construct

UVM end-of-test mechanism

Scoreboard in UVM

Verilog DUT System Verilog testbench: output to wire assignment 1s replaced with Xs