Category "hdl"

$readmemh doesn't read the values from data file

I'm using readmemh like: reg [11:0] rom [0:121]; initial $readmemh("x.data", rom); My x.data file looks like: line 1: 1 line 2: 10 . . . line 118: 1110101

I wrote this code in Verilog and there are no error messages, but it doesn't work

This is the module: module test (output reg [7:0] Q_out, input [2:0] data_in); always begin case (data_in) 3'b000: Q_out = 8'b10000000;