Verilog Code problem : "near "else": expecting: IDENT in" [duplicate]

Question

So i am creating an 8 bit left shift register in verilog where the 1 bit shift key is used as an enable input and clear is posedge triggered but have been receiving the following error and am unable identify the cause . "near "else": expecting: IDENT in"

module shift (CLK, CLR, SI, SO,shift); 
input  CLK,shift,SI,CLR; 
output SO; 
reg [7:0] tmp; 
reg SO;

always @(posedge CLK or posedge CLR or shift) 
begin 
if (CLR) 
  tmp = 8'b00000000; 
else
  
  if(shift) 
    tmp = {tmp[6:0], SI};
    SO=tmp[7];
  else
    tmp[0]=SI;
   
end
endmodule