Category "assembly"

Is it possible to have a switch/case with mips using a JumpTable for non sequential options?

I want to practice using switch/cases and JumpTables in MIPS. Currently, I am able to achieve a similar logic via stacking several BEQ commands after each other

Getting MS-DOS SMARTDrive version from interrupt call 2F/AX=4A10h/BX=0000h

I'm trying to write an assembly procedure to get the SMARTDrive version on a given system. The code to detect if SMARTDrive is loaded works correctly, but I ca

Is it possible to read a value from memory being written by another thread, so that it's neither the original nor final?

Suppose we have a variable in memory, which is constantly being updated by a thread of execution by doing something like MOV into it with alternating values (si

Assembly 2 digit 7 segment display

I have got a little problem of understanding how is suppose to work. Basically all what I need is to light up a led on each side of 7 segment display. They over

How to get the beginning address of a string instead of the address of a whole string

SORRY if i make you confuse about the question, but i don't know a better to describe it i'm trying to write a NASM program to reverse a string in place. i ha

IDA patching, How to add new code, create new variable?

I have a very basic knowledge about IDA and patching. From my understanding, I can change a line of code by doing Edit -> Patch program -> Assembly. But h

Tool to compare control flow of disassembly and C

Is there a tool to compare the control flow of some disassembly and some C? Here's my situation: I started with the disassembly (x86_64) of a function. In some

Apparent no-op in Rust assembly output?

I was studying the x86_64 assembly for the following function: /// Returns the greatest power of two less than or equal to `self`, or 0 otherwise. pub const fn

Bit-twiddling Wizardry for Index of Min or Max Element in XMM/YMM/ZMM

Is there an instruction or efficient branchless sequence of instructions to figure out the INDEX of (not the value of) the largest (or smallest) element of an u

What do the `uxtx` and `sxtx` extensions mean for 32-bit AArch64 `adds` instruction?

I'm looking at the following disassembled AArch64 instruction: 65 6E 20 2B adds w5, w19, w0, uxtx #3 According to the ARM manual, uxtx zero-extends w0 to an

How to create a text file that uses user input from Irvine library to write onto it

How do I create a text file that updates values inputted to by the user using Irvine's library? for example for my data I have: .data frstValue BYTE "Enter f

How to remove "noise" from GCC/clang assembly output?

I want to inspect the assembly output of applying boost::variant in my code in order to see which intermediate calls are optimized away. When I compile the fol

Integrating x86 assembly in C++ project for old MS-DOS system information program

I'm new to C++ programming and have always wanted to write a system information program for MS-DOS. I'm currently using the latest DigiMars C++ compiler and MA

Are RAX, RBX, RCX, RDX, RSI, RDI, RBP, RSP, R8-R15 interchangable?

Are x64 registers interchangable, in the sense that any instruction that works with one combination of them will work with any other? Is there performance diffe

How do you understand 'REX.W + B8+ rd io' form for x86-64 assembly?

I was originally trying to generate the bytes for an immediate move into a 64 bit register.The specific operation I wanted was mov rdi, 0x1337 Using https://ww

Null bytes in shellcode? Why does mov eax,1 machine code have bytes that are 00?

Going through the shellcode article on wikipedia, it gives an example as follows: B8 01000000 MOV EAX,1 // Set the register EAX to 0x000000001 To

relocation truncated to fit r_386_8 against .bss'

When I try to build my source into a 32-bit static executable for Linux with nasm -f elf -F dwarf -g loop.asm ld -m elf_i386 -o loop loop.o I get this R_386_

Can modern x86 implementations store-forward from more than one prior store?

In the case that a load overlaps two earlier stores (and the load is not fully contained in the oldest store), can modern Intel or AMD x86 implementations forwa

Why is a conditional move not vulnerable to Branch Prediction Failure?

After reading this post (answer on StackOverflow) (at the optimization section), I was wondering why conditional moves are not vulnerable for Branch Prediction

Why is XCHG reg, reg a 3 micro-op instruction on modern Intel architectures?

I'm doing micro-optimization on a performance critical part of my code and came across the sequence of instructions (in AT&T syntax): add %rax, %rbx mov %r