'Why logically equivalent lines got synthesized to totally different implementation?

Why these two lines synthesized to different logic? Are there any guidlines on how to code in order to get better results in terms of area?

module byte_extractor(
  input [256*8-1:0] data,
  input [7:0] sel,
  output reg [7:0] field
);
`ifdef VER1
  assign field = data[sel*8 +: 8];
`else
  assign field = data>>(sel*8);
`endif
endmodule

this is the synth script:

read_verilog -DVER1/2 byte_extractor.v
hierarchy -check
proc; opt;
techmap; opt
abc -liberty cmos_cells.lib
opt
opt_clean -purge
stat -liberty cmos_cells.lib

VER1 result:

   Number of cells:               1404
     MUX21                         153
     MUX41                         566
     NAND                          259
     NOR                           308
     NOT                           118

VER2 result:

  Number of cells:               1111
    MUX21                         126
    MUX41                         603
    NAND                          150
    NOR                           165
    NOT                            67
yosys


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