Verilog and SystemVerilog supported

Question

In the Yosys manual I read

C.108 read

-sv2005 -sv2009 -sv2012

load HDL designs Load the specified Verilog/SystemVerilog files. (Full SystemVerilog support is only available via Verific.)

C.113 read_verilog – read modules from Verilog file

-sv enable support for SystemVerilog features. (only a small subset of SystemVerilog is supported)

Is there a concise spec anywhere about this? If not, a guidline? Which Verilog and which SystemVerilog?

What is Verific?

In Clifford: A Free and Open Source Verilog-to-Bitstream Flow for iCE40 FPGAs Wolf says that "Verilog is pretty much everything from Verilog 2005". What not from Verilog 2005? Changes over time from this late 2015 lecture?

Answer 1

Verific is a reference to a commercial front-end provided by Verific Design Automation. There's a commercial version of Yosys sold as part of the Symbiotic EDA Suite that comes with this Verific front end installed. The Verific front end provides full VHDL+SV support as you see above.

The open source version of Yosys officially supports only Verilog 2005. Unofficially, several SV features have been added to it, (Enum, Typedef, etc.) and there's a beta VHDL support provided by GHDL-synth that's a work in progress.

Answer 2

It looks like the folks at Antmicro were kind enough to provide a frontend that allows direct reading of SystemVerilog. Check the following blogpost https://antmicro.com/blog/2022/02/simplifying-open-source-sv-synthesis-with-the-yosys-uhdm-plugin/