'Use only a subset of output port bits?

This is a general Verilog question. Say I have instantiated some module with a 32-bit output port, but I'm only interested in the low 8-bits.

wire [7:0] my_8bits;
some_module inst (
  ...
  .out_32bit_port(my_8bits);   // out_32bit_port is a 32-bit output port
);

This will generate a warning that the signal I have connected to the output port does not match the port size. Of course, in this case I am completely aware of what I've done and I can just ignore the warning.

How can I code this to eliminate all warnings?

verilog


Sources

This article follows the attribution requirements of Stack Overflow and is licensed under CC BY-SA 3.0.

Source: Stack Overflow

Solution Source

Related Questions

Verilog DUT System Verilog testbench: output to wire assignment 1s replaced with Xs

Verilog DUT System Verilog testbench: output to wire assignment 1s replaced with Xs

Difference in Clock Generation

How to write a module with variable number of ports in Verilog

code for clock generation in structural verilog

Understanding Verilog signal width parameter inheritance [duplicate]

Problems assigning to LEDs in a case block [duplicate]

I get a warning about $readmemh: Too many words in the file

Modulo adder output shows no change

how can i take slice from a fifo buffer?

How to change a register value without adding it to the sensitivity list?

Divide by a number which is not power of 2 in Verilog RTL coding

Generating number sequence in verilog (automat)

I wrote this code in Verilog and there are no error messages, but it doesn't work

FPGA bitfile acting different with the simulation