Unexpected ";" , expecting ")" near class handle

Question

So, I created my first system Verilog testbench by modifying the tutorial from https://verificationguide.com/systemverilog-examples/systemverilog-testbench-example-01/ ( In this tutorial a memory block is tested, I modified it for a simple AND gate).

There are seven files excluding the DUT file,

1. environment.sv
2. interface.sv
3. transactions.sv
4. generator.sv
5. testbench.sv ( topLevel testbench)
6. driver.sv
7. test.sv

I used Intel modelsim to compile these files.

While compiling, I got these errors in driver.sv and generator.sv

** Error: (vlog-13069) D:/Altera/Projects/AndGate/testbench/driver.sv(28): near ";": syntax error, unexpected ';', expecting '('.

** Error: (vlog-13069) D:/Altera/Projects/AndGate/testbench/generator.sv(4): near "trans": syntax error, unexpected IDENTIFIER, expecting ';' or ','.

Below are the corresponding files,

driver.sv

`define DRIV_IF mem_vif.DRIVER.driver_cb

class driver;

    int num_trans;
    virtual mem_intf mem_vif;
    
    mailbox gen2driv;
    
    function new(virtual mem_intf mem_vif, mailbox gen2driv);
        this.mem_vif = mem_vif;
        this.gen2driv = gen2driv;
    endfunction
    task reset();
      wait(mem_vif.reset);
      $display("--------- [DRIVER] Reset Started ---------");
      `DRIV_IF.A <= 0;
      `DRIV_IF.B <= 0;
      `DRIV_IF.C  <= 0;      
      wait(!mem_vif.reset);
      $display("--------- [DRIVER] Reset Ended ---------");
    endtask
    
    
    task drive();

            transaction trans;
            gen2driv.get(trans);
            $display("Num transactions : %0d", num_trans);
            @(posedge mem_vif.DRIVER.clk);
                `DRIV_IF.A <= trans.A;
                `DRIV_IF.B <= trans.B;
                 trans.C = `DRIV_IF.C;
                $display("\tA = %0h \tB = %0h \tC = %0h", trans.A, trans.B, `DRIV_IF.C);
                num_trans++;

    endtask
                
    

endclass

generator.sv

class generator;

    var rand transaction trans;
    mailbox gen2driv;
    int repeat_count;
    event ended;
    
    function new(mailbox gen2driv, event ended);
        this.gen2driv = gen2driv;
        this.ended = ended;
    endfunction
    
    task main();
        repeat(repeat_count) begin
            trans = new();
            if(!trans.randomize())$fatal("Random Generation failed");
            gen2driv.put(trans);

        end
        -> ended;
    endtask

endclass

Please, help me with this...

Answer 1

For future reference, it would really help to point to the line 28 and 4 in the respective files where the error is occurring as well as give the command line used to compile the code. But since I've seen this exact error before, I know it is because you put all of these files separately on your command line and not compiled together as a package.

Modelsim/Questa compiles every SystemVerilog file on the command line as a separate compilation unit. Identifiers declared in one compilation unit cannot be seen by other compilation units. When the generator and driver classes get compiled, it has no idea what transaction means and you get a syntax error. Modules and interfaces names exist in a separate namespace and the syntax where they are referenced allows them to used before their declarations have been compiled.

To remedy this, you could `include all you class files in testbench module, or the normal practice is putting them all in a package and importing the package. There is also a compilation mode where everything on the command line in one compilation unit, but that option is not scaleable as your designer get larger.

I also suggest reading these two posts I wrote:

https://blogs.sw.siemens.com/verificationhorizons/2010/07/13/package-import-versus-include/

https://blogs.sw.siemens.com/verificationhorizons/2009/05/07/programblocks/