'Understanding Verilog Code with two Clocks

I am pretty new to Verilog and I use it to verify some code from a simulation program. Right now I am struggeling if a verilog code snippet because the simulation programm uses 2 clocks ( one system clock and a pll of this ) where two hardware componentes work together, thus synchronize each other:

module something (input data)
reg vid;
always @(posegde sys_clk)
  vid <= data;

always @(posegde pll_clk)
  if (vid)
    // do something

When reading about non blocking assignments it says the evaluation of the left-hand side is postponed until other evaluations in the current time step are completed.

Intuitive I thought this means they are evaluated at the end of the time step, thus if data changes from 0 to 1 in sys_clk tick "A", this means at the end of "A" and the beginning of next sys_clk tick this value is in vid and so only after "A" the second always block ( of pll_clk) can read vid = 1

Is this how it works or did i miss something ?

Thank you :)

verilog

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'Understanding Verilog Code with two Clocks

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