The serial pin LVDSOUT for the LVDS SERDES IP instance must be pulled up to the top level and cannot fan out to anything else

Question

I have a compile error in my Quartus 20.3 project that appears to be within the Intel-generated LVDS SERDES IP. Can you provide additional insight into what the following error indicates as root cause? I believe the complaint is about a connection within the Intel IP: "The serial pin LVDSOUT for the LVDS SERDES IP instance dsi2_host_phy_top|phy_wrapper|tx_dphy_top|clk_lane_altera|lvds_0|core|arch_inst|channels[0].tx.serdes_dpa_isnt must be pulled up to the top level and cannot fan out to anything else."

This LVDS IP instance is configured as TX, 1 channel, SERDES factor=8 with external PLL.

Thanks.

Answer 1

There's a signal that comes out of that that SERDES IP block, specifically the LVDSOUT signal. The error is telling you that this signal cannot be connected to anything internal to your FPGA design. It can only be connected to the SERDES pin.

So for example, if you're trying to send the LVDSOUT pin to a flip-flop input, that could generate this error.

I would also recommend double-checking that the pin you're assigning to this signal is SERDES capable.