System Verilog macro using strings

Question

I would like to create a system verilog macro and pass a string variable to it. I've read another thread that uses define to define a string and pass thatSTRING_NAME which works but I need the following.

`define STRINGIFY(x) `"x`"

I want REG_PATH to be converted to the string which is used as a parameter.

`define mirror(REG_PATH) \
   $display(`STRINGIFY(REG_PATH)``other text);

When used I would like to pass the string using a string variable.

string register_path = "my string"
`mirror(register_path)

I have not tried this code but I know you can pass a string variable to a macro. That is why I use the STRINGIFY(REG_PATH).

Answer 1

If requirement is to just display , as string is already passed into the macro and it can be used directly without needing any conversion in the display.

define mirror(REG_PATH) \
   $display("%s ``other text",REG_PATH);

string register_path = "my string";

initial
   `mirror(register_path)

Also strings can be concatenated directly.

`define mirror(REG_PATH) \
   {REG_PATH," other text"}
initial
  $display(`mirror(register_path));

Option 3

 `define mirror(REG_PATH)  \
 $display("%s otherstring",$psprintf("%s",REG_PATH));
 initial
       `mirror(register_path)

Option 4

`define mirror(REG_PATH) \
    $psprintf("%s",REG_PATH)

initial
begin
  $display(`mirror(register_path));
end

Answer 2

I found the problem with this. Since the macro is a compile time feature, there will be no run time translation of a string. All I need to do is pass the object instead of a string because the thing I want to pass looks like a string but it's accualy an object. `define mirror(x) x.mirror_task() prepends the object to the mirror task in the objects class.