Page faults possible in worst case scenario

Question

I am taking the mft and in the sample test it has this question

Consider a virtual memory system running on a RISC CPU. Page tables are not locked in memory and may be swapped to disk. An 1w (load word) instruction reads one data word from memory; the address is the sum of the value in a register and an immediate constant stored in the instruction itself. Neither machine instruction nor page-table entries nor data words can cross a page boundary. In the worst case, how many page faults could be generated as a result of the fetch, decode, and execution of an 1w instruction?

Since this is a sample test I know the answer to this is 4. However, I have no idea how they got that number

Can someone explain what 4 page faults could occur and why?

I am reviewing this material and am extremely rusty on computer arcecture, so I might be missing something obvious

My best guess is that in both fetching and executing you get page faults for

1. The page table not being in memory (due to them being on disk)
2. The page containing lw not being in memory However, this seems overly simple. and I am not at all sure it is correct

Answer 1

I don't claim to be an expert, but I believe there would be three page faults as it first tries to page through the L1, L2, and L3 CPU caches before it makes the forth page fault through Memory.