'Makefile for multiple C programs
I've got a task to do a makefile of 5 different c programs. Let's call them 1.c, 2.c, 3.c, 4.c, 5.c
The code i've got is:
CC = gcc
CFLAGS = -Wall
LDFLAGS =
OBJFILES = 1.o 2.o 3.o 4.o 5.o
TARGET = 1 2 3 4 5
all: $(TARGET)
$(TARGET): $(OBJFILES)
$(CC) $(CFLAGS) -o $(TARGET) $(OBJFILES) $(LDFLAGS)
clean:
rm -f $(OBJFILES)
And the feedback is that I should do something with static template. How should I approach this problem?
Solution 1:[1]
You should let Make use its default rules. Your entire Makefile can be as simple as:
CC = gcc
CFLAGS = -Wall
all: 1 2 3 4 5
But if you are willing to require the user to type make 1 and make 2, etc., you can just delete the makefile completely. Let the user specify CC and CFLAGS in their environment if needed/desired.
Solution 2:[2]
I don't know what you mean by a static template, but your Makefile does not work. Try this change instead:
$(TARGET): $(OBJFILES)
$(CC) $(CFLAGS) -o $@ [email protected] $(LDFLAGS)
The drawback is that it compiles all five programs even if only one has to be rebuilt.
Sources
This article follows the attribution requirements of Stack Overflow and is licensed under CC BY-SA 3.0.
Source: Stack Overflow
| Solution | Source |
|---|---|
| Solution 1 | William Pursell |
| Solution 2 |
