'Is the following synthesizable?
Hi I am trying to create a verilog register that outputs its value only when the write signal is high else it is high impedance. Is the following synthesizable?
module R(data_from_bus,data_to_bus,clk,read,write);
input [7:0]data_from_bus;
input clk,read,write;
output reg[7:0] data_to_bus;
reg[7:0] r_reg;
always@(posedge clk)
begin
if (read==1)
r_reg<=data_from_bus;
end
always@(write)
begin
if (write==1)
data_to_bus=r_reg;
else
data_to_bus=8'bz;
end
endmodule
Solution 1:[1]
yes, it is synthesizable, but not necessarily doing what you want because of the questionable format.
here's a better (safer) version:
module R(data_from_bus,data_to_bus,clk,read,write);
input [7:0]data_from_bus;
input clk,read,write;
output data_to_bus;
reg[7:0] r_reg;
always@(posedge clk) begin
if (read)
r_reg<=data_from_bus;
else
r_reg<=r_reg;
end
wire[7:0] r_reg_wire;
assign r_reg_wire = r_reg;
assign data_to_bus = write ? r_reg_wire : 8'bz;
endmodule
the main problem of the one you posted is that you are not having an else statement for the first non-blocking assignment: (if (read == 1)) This might result in inferring a latch (but tools are most likely smart enough to fix it implicitly), which does the same thing in simulation as a flip-flop in simulation, but will mess with timing in real life deployment
a really good approach is to use 'always_ff' for registers assignment, 'always_comb' for combinational logic assignment, and 'always_latch' for intended latch (which is rarely used apart from really fishy timing case such as clock gating); but these keyword are only supported in SystemVerilog
Solution 2:[2]
Yes.
Here is the result of synthesizing the posted code in the free online tools available at the EDA Playground website, using Mentor Precision.
Please add r_reg to the sensitivity list for the combinational logic to assure the simulation and synthesis results agree. Use always @(*) to accomplish the same thing using a wildcard style approach.
Synthesis ran and produced no errors.
The log is shown below.
The last part of the log is a post synthesis Verilog netlist.
Note the tool used the FDRE primitive to implement the registers bits.
To repeat this process, see the reference design at:
https://www.edaplayground.com/x/2BmJ
- Copy the reference design to your EDA Playground account (assuming you have one;you should its free and helpfu) using the copy button.
- Paste the design you want to synthesize into the design.v tab.
- Run it by clicking the run button.
Log file
[2022-05-08 23:57:07 UTC] precision -shell -file run.do -fileargs "design.sv" && sed 's-$-<br>-g' precision.v > tmp.html && echo '<!DOCTYPE html> <html> <head> <style> body {font-family: monospace;} </style> </head> <body>' > tmp2.html && echo '</body> </html> ' > tmp3.html && cat tmp2.html tmp.html tmp3.html > precision.html
precision: Setting MGC_HOME to /usr/share/precision/Mgc_home ...
precision: Executing on platform: Derived from Red Hat Enterprise Linux 7.1 (Source) -- 5.4.0-107-generic -- x86_64
// Precision RTL Synthesis 64-bit 2021.1.0.4 (Production Release) Tue Jul 20 01:22:31 PDT 2021
//
// Copyright (c) Mentor Graphics Corporation, 1996-2021, All Rights Reserved.
// Portions copyright 1991-2008 Compuware Corporation
// UNPUBLISHED, LICENSED SOFTWARE.
// CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE
// PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
//
// Running on Linux runner@eaa22c631d4a #121-Ubuntu SMP Thu Mar 24 16:04:27 UTC 2022 5.4.0-107-generic x86_64
//
// Start time Sun May 8 19:57:09 2022
# -------------------------------------------------
# Info: [9569]: Logging session transcript to file /home/runner/precision.log
# Warning: [9508]: Results directory is not set. Use new_project, open_project, or set_results_dir.
# Info: [9577]: Input directory: /home/runner
# Info: [9572]: Moving session transcript to file /home/runner/precision.log
# Info: [9558]: Created project /home/runner/project_1.psp in folder /home/runner.
# Info: [9531]: Created directory: /home/runner/impl_1.
# Info: [9557]: Created implementation impl_1 in project /home/runner/project_1.psp.
# Info: [9578]: The Results Directory has been set to: /home/runner/impl_1/
# Info: [9569]: Logging project transcript to file /home/runner/impl_1/precision.log
# Info: [9569]: Logging suppressed messages transcript to file /home/runner/impl_1/precision.log.suppressed
# Info: [9552]: Activated implementation impl_1 in project /home/runner/project_1.psp.
# Info: [20026]: MultiProc: Precision will use a maximum of 8 logical processors.
# Info: [15302]: Setting up the design to use synthesis library "xca7.syn"
# Info: [585]: The global max fanout is currently set to 10000 for Xilinx - ARTIX-7.
# Info: [15328]: Setting Part to: "7A100TCSG324".
# Info: [15329]: Setting Process to: "1".
# Info: [7513]: The default input to Vivado place and route has been set to "Verilog".
# Info: [7512]: The place and route tool for current technology is Vivado.
# Info: [3052]: Decompressing file : /usr/share/precision/Mgc_home/pkgs/psr/techlibs/xca7.syn in /home/runner/impl_1/synlib.
# Info: [3022]: Reading file: /home/runner/impl_1/synlib/xca7.syn.
# Info: [645]: Loading library initialization file /usr/share/precision/Mgc_home/pkgs/psr/userware/xilinx_rename.tcl
# Info: [40000]: hdl-analyze, Release RTLC-Precision 2021a.12
# Info: [42003]: Starting analysis of files in library "work"
# Info: [41002]: Analyzing input file "/home/runner/design.sv" ...
# Info: [670]: Top module of the design is set to: R.
# Info: [668]: Current working directory: /home/runner/impl_1.
# Info: [40000]: RTLC-Driver, Release RTLC-Precision 2021a.12
# Info: [40000]: Last compiled on Jul 2 2021 08:23:33
# Info: [44512]: Initializing...
# Info: [44504]: Partitioning design ....
# Info: [40000]: RTLCompiler, Release RTLC-Precision 2021a.12
# Info: [40000]: Last compiled on Jul 2 2021 08:49:53
# Info: [44512]: Initializing...
# Info: [44522]: Root Module R: Pre-processing...
# Info: [44523]: Root Module R: Compiling...
# Warning: [45784]: "/home/runner/design.sv", line 11: Module R, Net(s) r_reg[7:0]: Although this signal is not part of the sensitivity list of this block, it is being read. This may lead to simulation mismatch.
# Info: [44842]: Compilation successfully completed.
# Info: [44856]: Total lines of RTL compiled: 17.
# Info: [44835]: Total CPU time for compilation: 0.0 secs.
# Info: [44513]: Overall running time for compilation: 1.0 secs.
# Info: [668]: Current working directory: /home/runner/impl_1.
# Info: [15334]: Doing rtl optimizations.
# Info: [671]: Finished compiling design.
# Info: [668]: Current working directory: /home/runner/impl_1.
# Info: [20026]: MultiProc: Precision will use a maximum of 8 logical processors.
# Info: [15002]: Optimizing design view:.work.R.INTERFACE
# Info: [15002]: Optimizing design view:.work.R.INTERFACE
# Info: [8010]: Gated clock transformations: Begin...
# Info: [8010]: Gated clock transformations: End...
# Info: [8053]: Added global buffer BUFGP for Port port:clk
# Info: [3027]: Writing file: /home/runner/impl_1/R.edf.
# Info: [3027]: Writing file: /home/runner/impl_1/R.xdc.
# Info: -- Writing file /home/runner/impl_1/R.tcl
# Info: [3027]: Writing file: /home/runner/impl_1/R.v.
# Info: -- Writing file /home/runner/impl_1/R.tcl
# Info: [671]: Finished synthesizing design.
# Info: [11019]: Total CPU time for synthesis: 0.8 s secs.
# Info: [11020]: Overall running time for synthesis: 1.0 s secs.
# Info: /home/runner/impl_1/precision_tech.sdc
# Info: [3027]: Writing file: /home/runner/precision.v.
# Info: [3027]: Writing file: /home/runner/precision.xdc.
# Info: -- Writing file /home/runner/impl_1/R.tcl
# Info: Info, Command 'auto_write' finished successfully
# Info: Num File Type Path
# Info: --------------------------------------------------------
# Info: 0 /home/runner/impl_1/R_area.rep
# Info: 1 /home/runner/impl_1/R_con_rep.sdc
# Info: 2 /home/runner/impl_1/R_tech_con_rep.sdc
# Info: 3 /home/runner/impl_1/R_fsm.rep
# Info: 4 /home/runner/impl_1/R_dsp_modes.rep
# Info: 5 /home/runner/impl_1/R_ram_modes.rep
# Info: 6 /home/runner/impl_1/R_env.htm
# Info: 7 /home/runner/impl_1/R.edf
# Info: 8 /home/runner/impl_1/R.v
# Info: 9 /home/runner/impl_1/R.xdc
# Info: 10 /home/runner/impl_1/R.tcl
# Info: ***************************************************************
# Info: Device Utilization for 7A100TCSG324
# Info: ***************************************************************
# Info: Resource Used Avail Utilization
# Info: ---------------------------------------------------------------
# Info: IOs 19 210 9.05%
# Info: Global Buffers 1 32 3.12%
# Info: LUTs 1 63400 0.00%
# Info: CLB Slices 1 15850 0.01%
# Info: Dffs or Latches 8 126800 0.01%
# Info: Block RAMs 0 135 0.00%
# Info: DSP48E1s 0 240 0.00%
# Info: ---------------------------------------------------------------
# Info: *****************************************************
# Info: Library: work Cell: R View: INTERFACE
# Info: *****************************************************
# Info: Number of ports : 19
# Info: Number of nets : 40
# Info: Number of instances : 29
# Info: Number of references to this view : 0
# Info: Total accumulated area :
# Info: Number of Dffs or Latches : 8
# Info: Number of LUTs : 1
# Info: Number of Primitive LUTs : 1
# Info: Number of accumulated instances : 29
# Info: *****************************
# Info: IO Register Mapping Report
# Info: *****************************
# Info: Design: work.R.INTERFACE
# Info: +---------------------+-----------+----------+----------+----------+
# Info: | Port | Direction | INFF | OUTFF | TRIFF |
# Info: +---------------------+-----------+----------+----------+----------+
# Info: | data_from_bus(7) | Input | | | |
# Info: +---------------------+-----------+----------+----------+----------+
# Info: | data_from_bus(6) | Input | | | |
# Info: +---------------------+-----------+----------+----------+----------+
# Info: | data_from_bus(5) | Input | | | |
# Info: +---------------------+-----------+----------+----------+----------+
# Info: | data_from_bus(4) | Input | | | |
# Info: +---------------------+-----------+----------+----------+----------+
# Info: | data_from_bus(3) | Input | | | |
# Info: +---------------------+-----------+----------+----------+----------+
# Info: | data_from_bus(2) | Input | | | |
# Info: +---------------------+-----------+----------+----------+----------+
# Info: | data_from_bus(1) | Input | | | |
# Info: +---------------------+-----------+----------+----------+----------+
# Info: | data_from_bus(0) | Input | | | |
# Info: +---------------------+-----------+----------+----------+----------+
# Info: | data_to_bus(7) | Output | | | |
# Info: +---------------------+-----------+----------+----------+----------+
# Info: | data_to_bus(6) | Output | | | |
# Info: +---------------------+-----------+----------+----------+----------+
# Info: | data_to_bus(5) | Output | | | |
# Info: +---------------------+-----------+----------+----------+----------+
# Info: | data_to_bus(4) | Output | | | |
# Info: +---------------------+-----------+----------+----------+----------+
# Info: | data_to_bus(3) | Output | | | |
# Info: +---------------------+-----------+----------+----------+----------+
# Info: | data_to_bus(2) | Output | | | |
# Info: +---------------------+-----------+----------+----------+----------+
# Info: | data_to_bus(1) | Output | | | |
# Info: +---------------------+-----------+----------+----------+----------+
# Info: | data_to_bus(0) | Output | | | |
# Info: +---------------------+-----------+----------+----------+----------+
# Info: | clk | Input | | | |
# Info: +---------------------+-----------+----------+----------+----------+
# Info: | read | Input | | | |
# Info: +---------------------+-----------+----------+----------+----------+
# Info: | write | Input | | | |
# Info: +---------------------+-----------+----------+----------+----------+
# Info: Total registers mapped: 0
# Info: [12022]: Design has no timing constraint and no timing information.
# Info: //
# Info: // Verilog description for cell R,
# Info: // Sun May 8 19:57:18 2022
# Info: //
# Info: // Precision RTL Synthesis, 64-bit 2021.1.0.4//
# Info: module R ( data_from_bus, data_to_bus, clk, read, write ) ;
# Info: input [7:0]data_from_bus ;
# Info: output [7:0]data_to_bus ;
# Info: input clk ;
# Info: input read ;
# Info: input write ;
# Info: wire [7:0]data_from_bus_int;
# Info: wire clk_int;
# Info: wire read_int, write_int, nx57998z1, nx198;
# Info: wire [7:0]r_reg;
# Info: OBUFT \data_to_bus_triBus1(0) (.O (data_to_bus[0]), .I (r_reg[0]), .T (
# Info: nx57998z1)) ;
# Info: OBUFT \data_to_bus_triBus1(1) (.O (data_to_bus[1]), .I (r_reg[1]), .T (
# Info: nx57998z1)) ;
# Info: OBUFT \data_to_bus_triBus1(2) (.O (data_to_bus[2]), .I (r_reg[2]), .T (
# Info: nx57998z1)) ;
# Info: OBUFT \data_to_bus_triBus1(3) (.O (data_to_bus[3]), .I (r_reg[3]), .T (
# Info: nx57998z1)) ;
# Info: OBUFT \data_to_bus_triBus1(4) (.O (data_to_bus[4]), .I (r_reg[4]), .T (
# Info: nx57998z1)) ;
# Info: OBUFT \data_to_bus_triBus1(5) (.O (data_to_bus[5]), .I (r_reg[5]), .T (
# Info: nx57998z1)) ;
# Info: OBUFT \data_to_bus_triBus1(6) (.O (data_to_bus[6]), .I (r_reg[6]), .T (
# Info: nx57998z1)) ;
# Info: OBUFT \data_to_bus_triBus1(7) (.O (data_to_bus[7]), .I (r_reg[7]), .T (
# Info: nx57998z1)) ;
# Info: IBUF write_ibuf (.O (write_int), .I (write)) ;
# Info: IBUF read_ibuf (.O (read_int), .I (read)) ;
# Info: IBUF \data_from_bus_ibuf(0) (.O (data_from_bus_int[0]), .I (
# Info: data_from_bus[0])) ;
# Info: IBUF \data_from_bus_ibuf(1) (.O (data_from_bus_int[1]), .I (
# Info: data_from_bus[1])) ;
# Info: IBUF \data_from_bus_ibuf(2) (.O (data_from_bus_int[2]), .I (
# Info: data_from_bus[2])) ;
# Info: IBUF \data_from_bus_ibuf(3) (.O (data_from_bus_int[3]), .I (
# Info: data_from_bus[3])) ;
# Info: IBUF \data_from_bus_ibuf(4) (.O (data_from_bus_int[4]), .I (
# Info: data_from_bus[4])) ;
# Info: IBUF \data_from_bus_ibuf(5) (.O (data_from_bus_int[5]), .I (
# Info: data_from_bus[5])) ;
# Info: IBUF \data_from_bus_ibuf(6) (.O (data_from_bus_int[6]), .I (
# Info: data_from_bus[6])) ;
# Info: IBUF \data_from_bus_ibuf(7) (.O (data_from_bus_int[7]), .I (
# Info: data_from_bus[7])) ;
# Info: INV ix57998z1315 (.O (nx57998z1), .I (write_int)) ;
# Info: BUFGP clk_ibuf (.O (clk_int), .I (clk)) ;
# Info: GND ps_gnd (.G (nx198)) ;
# Info: FDRE \reg_r_reg(7) (.Q (r_reg[7]), .C (clk_int), .CE (read_int), .D (
# Info: data_from_bus_int[7]), .R (nx198)) ;
# Info: FDRE \reg_r_reg(6) (.Q (r_reg[6]), .C (clk_int), .CE (read_int), .D (
# Info: data_from_bus_int[6]), .R (nx198)) ;
# Info: FDRE \reg_r_reg(5) (.Q (r_reg[5]), .C (clk_int), .CE (read_int), .D (
# Info: data_from_bus_int[5]), .R (nx198)) ;
# Info: FDRE \reg_r_reg(4) (.Q (r_reg[4]), .C (clk_int), .CE (read_int), .D (
# Info: data_from_bus_int[4]), .R (nx198)) ;
# Info: FDRE \reg_r_reg(3) (.Q (r_reg[3]), .C (clk_int), .CE (read_int), .D (
# Info: data_from_bus_int[3]), .R (nx198)) ;
# Info: FDRE \reg_r_reg(2) (.Q (r_reg[2]), .C (clk_int), .CE (read_int), .D (
# Info: data_from_bus_int[2]), .R (nx198)) ;
# Info: FDRE \reg_r_reg(1) (.Q (r_reg[1]), .C (clk_int), .CE (read_int), .D (
# Info: data_from_bus_int[1]), .R (nx198)) ;
# Info: FDRE \reg_r_reg(0) (.Q (r_reg[0]), .C (clk_int), .CE (read_int), .D (
# Info: data_from_bus_int[0]), .R (nx198)) ;
# Info: endmodule
Sources
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Source: Stack Overflow
| Solution | Source |
|---|---|
| Solution 1 | |
| Solution 2 |