'Is L2 Cache Miss equivalent to "L2 Data Cache Refill" on ARMv7 A15?

I am trying to determine which hardware counters available on the ARM Cortex A15 processor are the correct ones to use for determining system-wide L2 cache misses.

My application here is a kernel-level voltage-frequency governor (i.e. it could substitute for the ondemand governor). Because I need access to performance counters at the system level and not attached to a particular program runtime, I am not using existing utilities such as PAPI or Linux's perf tool. From my past experiences with both I understand that these are better used to monitor the performance stats for a particular program or instrumented binary.

I have implemented a kernel module that periodically updates several hardware counter values to sysfs endpoints. The resources I have used include:

The hardware counter I am currently using to measure L2 misses is event 0x17: "L2 data cache refill". Printing this value consistently gives 0, even when running data-heavy benchmarks. Is there a different event or set of events I should be using to determine L2 cache misses? Perhaps 0x13, "Data memory accesses", or some composite of events?

It is very possible that the root of my question is a misunderstanding of "L2 data cache refills", but I have not been able to find a clarification on this through documentation and stack overflow searches.

EDIT: I have found that L2 refills was reading 0 because the 5th hardware counter for some reason is not working as expected; re-assigning L2 refills to a different counter has resolved this particular issue.

EDIT 2: That 5th hardware counter was not function because I had not enabled that many. Silly me.



Solution 1:[1]

Quote from a different ARM manual implies refills are not just misses:

L1 data cache refill: "This event counts all allocations into the L1 cache. This includes read linefills, store linefills, and prefetch linefills."

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Source: Stack Overflow

Solution Source
Solution 1 Sorin