'Is indexing into an array with a signal synthesizable in verilog?

Are there any problems with synthesizing the following?:

 // Read entry
  assign entry[7:0] = my_array[read_address[10:0]][7:0];

Where read_address is a signal being used to read my_array.

I'm used to AND-OR logic for reading an array but I was wondering if the above is 1) synthesizable and 2) what kind of logic it would create?

verilog synthesis

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