Instantiating error Verilog (No objects found matching '/elevator_controller_tb/)

Question

I am a novice in Verilog, so I am not aware of instantiating process instead I combined my code with the testbench but I am facing some error in it. Here is the error when I tried simulating it (No objects found matching '/elevator_controller_tb/)

here are the two codes👇

module elevator_controller (request_floor,in_current_floor,clk,reset,complete, direction, over_time,over_weight,weigh_alert,door_alert,out_current_floor);

//Input pins
input [7:0] request_floor;
input [7:0] in_current_floor;
input clk;
input reset;
input over_time;
input over_weight;

//Output pins
output direction;
output complete;
output door_alert;
output weigh_alert;
output [7:0] out_current_floor;

//registerparameters

reg r_direction;
reg r_complete;
reg r_door_alert;
reg r_weigh_alert;
reg [7:0] r_out_current_floor;

//clock generator register
reg [12:0] clk_count;
reg clk_200;
reg clk_trigger;

//match pins and registers
assign direction=r_direction;
assign complete=r_complete;
assign door_alert=r_door_alert;
assign weigh_alert=r_weigh_alert;
assign out_current_floor=r_out_current_floor;

//initialization

always@(negedge reset) begin
clk_200=1'b0;
clk_count=0;
clk_trigger=1'b0;

//reset clock registers
r_complete=1'b0;
r_door_alert=1'b0;
r_weigh_alert=1'b0;
end

//clock generator block
always@(posedge clk) begin
if(clk_trigger) begin
clk_count=clk_count+1;
end
if(clk_count==5000)begin
clk_200=~clk_200;
clk_count=0;
end
end

always@(request_floor) begin
clk_trigger=1;
clk_200=~clk_200;

//trigger the clock generator

r_out_current_floor<=in_current_floor;

end


always@(posedge clk)begin

if(!reset && !over_time && !over_weight)begin

//case1

if (request_floor> r_out_current_floor) begin
r_direction=1'b1;
r_out_current_floor<=r_out_current_floor<<1;
end

else if(request_floor<r_out_current_floor) begin
r_direction=1'b0;
r_out_current_floor=r_out_current_floor>>1;

end
else if (request_floor == r_out_current_floor) begin
r_complete=1;
r_direction=0;
end
end

else if (!reset && over_time) begin
r_door_alert=1;
r_complete=1;
r_weigh_alert=0;
r_direction=0;
r_out_current_floor <= r_out_current_floor;
end

else if (!reset && over_weight) begin
r_door_alert=0;
r_weigh_alert=1;
r_complete=1;
r_direction=0;
r_out_current_floor <= r_out_current_floor;
end
end
endmodule

test bench👇

`timescale 1ns/1ns
module elevator_controller_tb;

reg[7:0] request_floor;
reg[7:0] in_current_floor;
reg clk;
reg reset;
reg over_time;
reg over_weight;

wire direction;
wire complete;
wire door_alert;
wire weigh_alert;
wire [7:0] out_current_floor;

elevator_controller elevator_controller_test(
.request_floor(request_floor),
.in_current_floor(in_current_floor),
.clk(clk),
.reset(reset),
.direction(direction),
.out_current_floor(out_current_floor),
.complete (complete),
.over_time(over_time),
.over_weight(over_weight),
.door_alert(door_alert),
.weigh_alert(weigh_alert)); 

//generate the clock and test the circuit with different inputs

initial 
    begin
#0 clk=1'b0; reset = 1'b1; over_time = 1'b0; over_weight = 1'b0;
#50 reset = 1'b0;
#50 reset = 1'b1;
#50 request_floor = 8'b00000001; in_current_floor = 8'b10000000;
#50 reset = 1;
#50 reset = 0;
#50 request_floor = 8'b00000001; in_current_floor = 8'b10000000;
#50 reset = 1'b1;
#50 reset = 1'b0;
#50 over_time = 1;
#50 reset = 1'b1;
#50 reset = 1'b0;
#50 over_weight = 1;
#50 reset = 1'b1;
     end
   always #50 clk = ~clk;
endmodule

Can someone pls point out my mistake